Sylpheed/tools/ppc-manual/vmx/vpkshus.md

vpkshus — Vector Pack Signed Half Word Unsigned Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000010e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vpkshus	vpkshus	—	Vector Pack Signed Half Word Unsigned Saturate
vpkshus128	vpkshus128	—	Vector128 Pack Signed Half Word Unsigned Saturate

Syntax

vpkshus [VD], [VA], [VB]
vpkshus128 [VD], [VA], [VB]

Encoding

vpkshus — form VX

• Opcode word: 0x1000010e
• Primary opcode (bits 0–5): 4
• Extended opcode: 270
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vpkshus128 — form VX128

• Opcode word: 0x14000240
• Primary opcode (bits 0–5): 5
• Extended opcode: 576
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vpkshus: read; vpkshus128: read	Source A vector register.
VB	vpkshus: read; vpkshus128: read	Source B vector register.
VD	vpkshus: write; vpkshus128: write	Destination vector register.
VSCR	vpkshus: write; vpkshus128: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vpkshus

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

vpkshus128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vpkshus: VSCR[SAT] may be stickied on saturating vector operations.
• vpkshus128: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vpkshus

• Canary XML: tools/ppc-instructions.xml — search for mnem="vpkshus"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1939
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:407
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:574

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vpkshus(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vpkshus_(f, i.VX.VD, i.VX.VA, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1924) ──
int InstrEmit_vpkshus_(PPCHIRBuilder& f, uint32_t vd, uint32_t va,
                       uint32_t vb) {
  // Vector Pack Signed Halfword Unsigned Saturate
  // Convert VA and VB from signed shorts to unsigned saturated bytes then
  // concat:
  // for each i in VA + VB:
  //   i = uint8_t(Clamp(EXTS(int16_t(i)), 0, 255))
  // dest = VA | VB (lower 8bit values)
  Value* v = f.Pack(f.LoadVR(va), f.LoadVR(vb),
                    PACK_TYPE_8_IN_16 | PACK_TYPE_IN_SIGNED |
                        PACK_TYPE_OUT_UNSIGNED | PACK_TYPE_OUT_SATURATE);
  f.StoreSAT(f.DidSaturate(v));
  f.StoreVR(vd, v);
  return 0;
}

vpkshus128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vpkshus128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1942
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:408
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:735

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vpkshus128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vpkshus_(f, VX128_VD128, VX128_VA128, VX128_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1924) ──
int InstrEmit_vpkshus_(PPCHIRBuilder& f, uint32_t vd, uint32_t va,
                       uint32_t vb) {
  // Vector Pack Signed Halfword Unsigned Saturate
  // Convert VA and VB from signed shorts to unsigned saturated bytes then
  // concat:
  // for each i in VA + VB:
  //   i = uint8_t(Clamp(EXTS(int16_t(i)), 0, 255))
  // dest = VA | VB (lower 8bit values)
  Value* v = f.Pack(f.LoadVR(va), f.LoadVR(vb),
                    PACK_TYPE_8_IN_16 | PACK_TYPE_IN_SIGNED |
                        PACK_TYPE_OUT_UNSIGNED | PACK_TYPE_OUT_SATURATE);
  f.StoreSAT(f.DidSaturate(v));
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

• Signed half-word → unsigned byte saturating pack. Each of the 16 input half-word lanes (8 from VA, 8 from VB) is interpreted as int16 and clamped to [0, 255]. Negative values → 0; values above 255 → 255. Clamping any lane sticky-sets VSCR[SAT].
• Lane-count doubling. 16 half-word lanes → 16 byte lanes, VA filling VD.b[0..7] and VB filling VD.b[8..15].
• Difference from vpkshss. Both take signed half-words; shss clamps to int8, shus clamps to uint8. Choose shus when the signed negative half is not physically meaningful (e.g. after subtracting a clamped-at-zero value).
• VSCR[SAT] is sticky.
• No Rc, no XER / FPSCR.
• VMX128 sibling vpkshus128. Same behaviour with wider register file.

Related Instructions

• vpkshss — signed → signed clamp.
• vpkuhus — unsigned input → unsigned byte.
• vpkuhum — unsigned input, truncating (modulo) pack.
• vpkswus — the word → half-word signed→unsigned analogue.
• vupkhub-family unpacks (if present) — the inverse.

IBM Reference

• AIX 7.3 — vpkshus (Vector Pack Signed Half Word Unsigned Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting