Sylpheed/tools/ppc-manual/vmx/vrfim.md

vrfim — Vector Round to Floating-Point Integer toward -Infinity

Category: VMX (Altivec) · Form: VX · Opcode: 0x100002ca

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vrfim	vrfim	—	Vector Round to Floating-Point Integer toward -Infinity
vrfim128	vrfim128	—	Vector128 Round to Floating-Point Integer toward -Infinity

Syntax

vrfim [VD], [VB]
vrfim128 [VD], [VB]

Encoding

vrfim — form VX

• Opcode word: 0x100002ca
• Primary opcode (bits 0–5): 4
• Extended opcode: 714
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vrfim128 — form VX128_3

• Opcode word: 0x18000330
• Primary opcode (bits 0–5): 6
• Extended opcode: 816
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (6)
6–10	VD128l	destination low 5 bits
11–15	IMM	5-bit immediate
16–20	VB128l	source B low 5 bits
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VB	vrfim: read; vrfim128: read	Source B vector register.
VD	vrfim: write; vrfim128: write	Destination vector register.

Register Effects

vrfim

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vrfim128

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vrfim

• Canary XML: tools/ppc-instructions.xml — search for mnem="vrfim"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1216
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:423
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:611

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vrfim(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vrfim_(f, i.VX.VD, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1210) ──
int InstrEmit_vrfim_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) {
  // (VD) <- RndToFPInt32Floor(VB)
  Value* v = f.Round(f.LoadVR(vb), ROUND_TO_MINUS_INFINITY);
  f.StoreVR(vd, v);
  return 0;
}

vrfim128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vrfim128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1219
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:424
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:775

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vrfim128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vrfim_(f, VX128_3_VD128, VX128_3_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1210) ──
int InstrEmit_vrfim_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) {
  // (VD) <- RndToFPInt32Floor(VB)
  Value* v = f.Round(f.LoadVR(vb), ROUND_TO_MINUS_INFINITY);
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

• Round toward minus-infinity (floor). Each 32-bit float lane of VB is rounded down to the nearest integer value still representable as a float. 3.2 → 3.0, −3.2 → −4.0.
• IEEE-754 binary32 output; VSCR[NJ] honoured (denormal flush-to-zero).
• Integer-too-big lanes are a no-op: values already ≥ 2²³ in magnitude are all-integer and unchanged.
• NaN propagation. NaN input → NaN output. ±∞ → ±∞.
• No VSCR[SAT], no FPSCR update. No "inexact" trap flag; this is the VMX rounding variant that deliberately ignores FPSCR's rounding mode.
• Big-endian lane indexing.
• VMX128 sibling vrfim128.

Related Instructions

• vrfin — round to nearest (ties-to-even).
• vrfip — round toward +∞ (ceiling).
• vrfiz — round toward zero (truncate).
• vctsxs, vctuxs — float → fixed-point integer conversion with explicit scale.

IBM Reference

• AIX 7.3 — vrfim (Vector Round to Floating-Point Integer toward Minus Infinity)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Arithmetic