Sylpheed/tools/ppc-manual/vmx/vrsqrtefp.md

vrsqrtefp — Vector Reciprocal Square Root Estimate Floating Point

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000014a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vrsqrtefp	vrsqrtefp	—	Vector Reciprocal Square Root Estimate Floating Point
vrsqrtefp128	vrsqrtefp128	—	Vector128 Reciprocal Square Root Estimate Floating Point

Syntax

vrsqrtefp [VD], [VB]
vrsqrtefp128 [VD], [VB]

Encoding

vrsqrtefp — form VX

• Opcode word: 0x1000014a
• Primary opcode (bits 0–5): 4
• Extended opcode: 330
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vrsqrtefp128 — form VX128_3

• Opcode word: 0x18000670
• Primary opcode (bits 0–5): 6
• Extended opcode: 1648
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (6)
6–10	VD128l	destination low 5 bits
11–15	IMM	5-bit immediate
16–20	VB128l	source B low 5 bits
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VB	vrsqrtefp: read; vrsqrtefp128: read	Source B vector register.
VD	vrsqrtefp: write; vrsqrtefp128: write	Destination vector register.

Register Effects

vrsqrtefp

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vrsqrtefp128

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vrsqrtefp

• Canary XML: tools/ppc-instructions.xml — search for mnem="vrsqrtefp"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1347
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:436
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:578

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vrsqrtefp(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vrsqrtefp_(f, i.VX.VD, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1338) ──
int InstrEmit_vrsqrtefp_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) {
  // (VD) <- 1 / sqrt(VB)
  // There are a lot of rules in the Altivec_PEM docs for handlings that
  // result in nan/infinity/etc. They are ignored here. I hope games would
  // never rely on them.
  Value* v = f.RSqrt(f.LoadVR(vb));
  f.StoreVR(vd, v);
  return 0;
}

vrsqrtefp128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vrsqrtefp128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1350
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:437
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:780

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vrsqrtefp128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vrsqrtefp_(f, VX128_3_VD128, VX128_3_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1338) ──
int InstrEmit_vrsqrtefp_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) {
  // (VD) <- 1 / sqrt(VB)
  // There are a lot of rules in the Altivec_PEM docs for handlings that
  // result in nan/infinity/etc. They are ignored here. I hope games would
  // never rely on them.
  Value* v = f.RSqrt(f.LoadVR(vb));
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

• Lane-wise reciprocal-square-root estimate. Each 32-bit float lane of VB is approximated by 1.0 / sqrt(VB[i]). The PowerPC spec permits a 12-bit estimate; Canary's x64 backend also returns an estimate rather than the exact value, from table-driven helpers (vrsqrtefp_scalar_helper / vrsqrtefp_vector_helper, built on GetNormalVRsqrteTable). Whether that matches Xenon bit-for-bit is unverified.
• Standard Newton iteration (Quake-style): x₁ = x₀ * (1.5 − 0.5 * VB * x₀²). One pass produces ~24 bits of precision — essentially indistinguishable from a true 1/sqrt.
• Negative input is a trap in math terms but not in ISA terms: the hardware returns a QNaN. sqrt(−x) for x > 0 → QNaN. Zero produces +∞ (and may sticky-set no bits).
• IEEE-754 binary32; VSCR[NJ] honoured.
• No VSCR[SAT], no FPSCR update, no exception.
• Big-endian lane indexing.
• VMX128 sibling vrsqrtefp128.

Related Instructions

• vrefp — plain reciprocal estimate.
• vmaddfp, vnmsubfp — the Newton iteration primitives.
• vexptefp, vlogefp — the other transcendental estimates.

IBM Reference

• AIX 7.3 — vrsqrtefp (Vector Reciprocal Square Root Estimate Floating Point)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Arithmetic