Sylpheed/tools/ppc-manual/vmx/vsubsbs.md

vsubsbs — Vector Subtract Signed Byte Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000700

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vsubsbs	vsubsbs	—	Vector Subtract Signed Byte Saturate

Syntax

vsubsbs [VD], [VA], [VB]

Encoding

vsubsbs — form VX

• Opcode word: 0x10000700
• Primary opcode (bits 0–5): 4
• Extended opcode: 1792
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vsubsbs: read	Source A vector register.
VB	vsubsbs: read	Source B vector register.
VD	vsubsbs: write	Destination vector register.
VSCR	vsubsbs: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vsubsbs

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vsubsbs: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vsubsbs

• Canary XML: tools/ppc-instructions.xml — search for mnem="vsubsbs"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1679
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:471
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:661

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vsubsbs(PPCHIRBuilder& f, const InstrData& i) {
  // (VD) <- clamp(EXTS(VA) + ¬EXTS(VB) + 1, -128, 127)
  Value* v = f.VectorSub(f.LoadVR(i.VX.VA), f.LoadVR(i.VX.VB), INT8_TYPE,
                         ARITHMETIC_SATURATE);
  f.StoreSAT(f.DidSaturate(v));
  f.StoreVR(i.VX.VD, v);
  return 0;
}

Special Cases & Edge Conditions

• Signed-byte saturating subtract. VD.b[i] = clamp_int8(VA.b[i] − VB.b[i]). Each lane computed as int8; any lane that goes below −128 or above +127 is clamped and sticky-sets VSCR[SAT]. Canary clamps the lanes (VectorSub with ARITHMETIC_SATURATE) but never records SAT (x64 DID_SATURATE is a stub).
• Sticky VSCR[SAT]. Once set it remains set until explicit mtvscr clear.
• Big-endian byte lanes.
• No Rc, no XER.
• No VMX128 sibling.
• Compare with vsububs for the unsigned variant, or vsububm for modulo wrap.

Related Instructions

• vaddsbs — signed byte saturating add.
• vsububs, vsububm — unsigned byte sub (saturating / modulo).
• vsubshs, vsubsws — signed saturating subtracts at wider lane widths.

IBM Reference

• AIX 7.3 — vsubsbs (Vector Subtract Signed Byte Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic