9bfe96e44d
- Category pages linked each family as `<slug>.md`, relative to categories/, where no family page lives. They now link `../<category>/<slug>.md`. - Form pages linked a member into its *own* category directory, so every VMX128 sibling (`vsldoi128`) pointed at vmx128/ although its family page is under vmx/. They now link into the family's directory. - Hand-written "Related" and sibling mentions linked other categories' pages as if they were in the same directory. 109 are retargeted through the page index; 29 that pointed a family page at itself (`vrefp128` on vrefp.md) and 6 naming instructions the manual has no page for are plain text now. Regenerated at the existing Canary pin (f21ebd49e): upstream has moved on, and re-pinning belongs in its own change. The generator reports 0 family pages changed and is idempotent; the only dead links left are TEMPLATE.md's placeholders. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
4.7 KiB
4.7 KiB
vupkhsh — Vector Unpack High Signed Half Word
Category: VMX (Altivec) · Form: VX · Opcode:
0x1000024e
Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
|---|---|---|---|
vupkhsh |
vupkhsh |
— | Vector Unpack High Signed Half Word |
Syntax
vupkhsh [VD], [VB]
Encoding
vupkhsh — form VX
- Opcode word:
0x1000024e - Primary opcode (bits 0–5):
4 - Extended opcode:
590 - Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode (4) |
| 6–10 | VRT/VD |
destination vector register |
| 11–15 | VRA/VA |
source A vector register |
| 16–20 | VRB/VB |
source B vector register |
| 21–31 | XO |
extended opcode (11 bits) |
Operands
| Field | Role | Description |
|---|---|---|
VB |
vupkhsh: read | Source B vector register. |
VD |
vupkhsh: write | Destination vector register. |
Register Effects
vupkhsh
- Reads (always):
VB - Reads (conditional): none
- Writes (always):
VD - Writes (conditional): none
Status-Register Effects
No condition-register or status-register effects.
Operation (pseudocode)
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
C Translation Example
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
Implementation References
vupkhsh
- Canary XML:
tools/ppc-instructions.xml— search formnem="vupkhsh" - Canary emitter:
src/xenia/cpu/ppc/ppc_emit_altivec.cc:2007 - Sylpheed opcode:
crates/sylpheed-ppc/src/opcode.rs:489 - Sylpheed decoder:
crates/sylpheed-ppc/src/decoder.rs:603
Canary emitter (frozen snapshot @ f21ebd49e9)
int InstrEmit_vupkhsh(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_vupkhsh_(f, i.VX.VD, i.VX.VB);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1998) ──
int InstrEmit_vupkhsh_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) {
// Vector Unpack High Signed Halfword
// halfwords 0-3 expanded to words 0-3 and sign extended
Value* v =
f.Unpack(f.LoadVR(vb), PACK_TYPE_TO_HI | PACK_TYPE_16_IN_32 |
PACK_TYPE_IN_SIGNED | PACK_TYPE_OUT_SIGNED);
f.StoreVR(vd, v);
return 0;
}
Special Cases & Edge Conditions
- Sign-extend the high 4 of 8 half-words into words.
VB.h[0..3]are each reinterpreted asint16and sign-extended toint32inVD.w[0..3]. - Inverse of the high half of
vpkswss(within theint16range). - Big-endian lane ordering.
- No saturation, no flags, no VSCR effect.
- VMX128 sibling
vupkhsh128.
Related Instructions
vupklsh— unpacks the low 4 half-words.vupkhsb,vupklsb— byte → half-word sign-extending unpacks.vpkswss,vpkswus— the inverse pack (saturating).