Sylpheed/tools/ppc-manual/vmx128/vmaddcfp128.md

vmaddcfp128 — Vector128 Multiply Add Floating Point

Category: VMX128 · Form: VX128 · Opcode: 0x14000110

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmaddcfp128	vmaddcfp128	—	Vector128 Multiply Add Floating Point

Syntax

vmaddcfp128 [VD], [VA], [VD], [VB]

Encoding

vmaddcfp128 — form VX128

• Opcode word: 0x14000110
• Primary opcode (bits 0–5): 5
• Extended opcode: 272
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vmaddcfp128: read	Source A vector register.
VD	vmaddcfp128: read; vmaddcfp128: write	Destination vector register.
VB	vmaddcfp128: read	Source B vector register.

Register Effects

vmaddcfp128

• Reads (always): VA, VD, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmaddcfp128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vmaddcfp128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:806
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:347
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:729

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vmaddcfp128(PPCHIRBuilder& f, const InstrData& i) {
  // (VD) <- ((VA) * (VD)) + (VB)
  return InstrEmit_vmaddfp_(f, VX128_VD128, VX128_VA128, VX128_VB128,
                            VX128_VD128);
}

Special Cases & Edge Conditions

• Xbox-specific fused multiply-add variant. Canary computes each lane as VD[i] = VA[i] * VD[i] + VB[i] (its comment: (VD) <- ((VA) * (VD)) + (VB)) — VD is both a factor and the destination. This is not the standard vmaddfp operand order: VD stands where vmaddfp has VC, and VB is the addend. Whether Xenon uses the same order has not been checked on hardware.
• Fused, single-rounding. Canary emits MulAdd, which is vfmadd213ps on FMA3 hosts and vmulps + vaddps (two roundings) otherwise, so the bit-exact result depends on host support.
• IEEE-754 binary32 lanes; VSCR[NJ] honoured.
• No VSCR[SAT], no FPSCR update.
• NaN propagation per IEEE-754.
• VMX128 register-fusion (7-bit IDs on VA, VB, VD).
• No IBM AIX entry — Xenon-only.
• No Rc, no XER.

Related Instructions

• vmaddfp, vmaddfp128 — standard fused (VA × VC) + VB.
• vmulfp128 — plain lane-wise float multiply.
• vnmsubfp — negative-multiply-subtract.
• vmsum3fp128, vmsum4fp128 — dot-product reductions.

IBM Reference

• No IBM AIX entry — this is an Xbox 360 VMX128 extension. Its semantics differ from the base Altivec vmaddfp in the operand order (accumulator in VD, not VC).
• Xbox 360 XDK, Altivec-128 (VMX128) extensions.
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Arithmetic for the base FMA semantics.