Sylpheed/tools/ppc-manual/alu/cmpl.md

cmpl — Compare Logical

Category: Integer ALU · Form: X · Opcode: 0x7c000040

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
cmpl	cmpl	—	Compare Logical

Syntax

cmpl [CRFD], [L], [RA], [RB]

Encoding

cmpl — form X

• Opcode word: 0x7c000040
• Primary opcode (bits 0–5): 31
• Extended opcode: 32
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
L	cmpl: read	Operand-length bit for compare instructions (0 ⇒ 32-bit, 1 ⇒ 64-bit).
RA	cmpl: read	Source GPR (r0–r31).
RB	cmpl: read	Source GPR.
CRFD	cmpl: write	CR destination field (crf, 0–7).

Register Effects

cmpl

• Reads (always): L, RA, RB
• Reads (conditional): none
• Writes (always): CRFD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

if L = 0 then a,b <- (RA)[32:63], (RB)[32:63]
else             a,b <- (RA), (RB)
CR[BF] <- unsigned_compare(a, b) || XER[SO]

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

cmpl

• Canary XML: tools/ppc-instructions.xml — search for mnem="cmpl"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:579
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:29
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:876

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_cmpl(PPCHIRBuilder& f, const InstrData& i) {
  // if L = 0 then
  //   a <- i32.0 || (RA)[32:63]
  //   b <- i32.0 || (RB)[32:63]
  // else
  //   a <- (RA)
  //   b <- (RB)
  // if a <u b then
  //   c <- 0b100
  // else if a >u b then
  //   c <- 0b010
  // else
  //   c <- 0b001
  // CR[4×BF+32:4×BF+35] <- c || XER[SO]
  uint32_t BF = i.X.RT >> 2;
  uint32_t L = i.X.RT & 1;
  Value* lhs;
  Value* rhs;
  if (L) {
    lhs = f.LoadGPR(i.X.RA);
    rhs = f.LoadGPR(i.X.RB);
  } else {
    lhs = f.Truncate(f.LoadGPR(i.X.RA), INT32_TYPE);
    rhs = f.Truncate(f.LoadGPR(i.X.RB), INT32_TYPE);
  }
  f.UpdateCR(BF, lhs, rhs, false);
  return 0;
}

Special Cases & Edge Conditions

• Unsigned compare. Treats both operands as unsigned magnitudes. The simplified mnemonics are cmplw (L=0) and cmpld (L=1).
• L = 0: 32-bit operands. Canary truncates both registers to 32 bits before the unsigned compare, so the high 32 bits of RA/RB are ignored — this matches spec (RA)[32:63] semantics. Most Xbox 360 code uses this mode.
• L = 1: full 64-bit unsigned compare. Used in 64-bit pointer arithmetic; rare in game code but appears in kernel-side helpers.
• SO is copied from XER[SO]. cmpl does not clear or set sticky overflow; it just exposes the current SO in the destination CR field's SO slot.
• BF is a CR field 0–7. Same convention as cmp. Two consecutive cmpl instructions with the same BF simply overwrite the previous result.
• Common signed/unsigned bug. Misusing cmp instead of cmpl (or vice versa) for pointer comparisons is the canonical bug in PPC porting; pointers are always unsigned in C semantics. Always cross-check the comparison polarity in disassembly.
• No Rc/OE and no GPR write — purely a CR-field producer.

Related Instructions

• cmp — signed register compare.
• cmpli — unsigned compare against a 16-bit immediate.
• cmpi — signed immediate compare.
• cmplw, cmpld (simplified) — preferred forms in disassembly.
• mcrxr — clear sticky overflow.

IBM Reference

• AIX 7.3 — cmpl (Compare Logical)
• AIX 7.3 — cmplw / cmpld (simplified mnemonics)