Sylpheed/tools/ppc-manual/alu/extsbx.md

extsbx — Extend Sign Byte

Category: Integer ALU · Form: X · Opcode: 0x7c000774

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
extsb	extsbx	—	Extend Sign Byte
extsb.	extsbx	Rc=1	Extend Sign Byte

Syntax

extsb[Rc] [RA], [RS]

Encoding

extsbx — form X

• Opcode word: 0x7c000774
• Primary opcode (bits 0–5): 31
• Extended opcode: 954
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	extsbx: read	Source GPR (alias for RD in some stores).
RA	extsbx: write	Source GPR (r0–r31).
CR	extsbx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

extsbx

• Reads (always): RS
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• extsbx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RA <- EXTS_8_to_64((RS)[56:63])

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

extsbx

• Canary XML: tools/ppc-instructions.xml — search for mnem="extsbx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:714
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:60
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:964

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_extsbx(PPCHIRBuilder& f, const InstrData& i) {
  // s <- (RS)[56]
  // RA[56:63] <- (RS)[56:63]
  // RA[0:55] <- i56.s
  Value* rt = f.LoadGPR(i.X.RT);
  rt = f.SignExtend(f.Truncate(rt, INT8_TYPE), INT64_TYPE);
  f.StoreGPR(i.X.RA, rt);
  if (i.X.Rc) {
    f.UpdateCR(0, rt);
  }
  return 0;
}

Special Cases & Edge Conditions

• Sign-extends the low 8 bits of RS to 64 bits. Bit 56 of RS (the sign bit of the byte) becomes bits 0–55 of RA; bits 56–63 are copied verbatim.
• Common after a byte load. lbz zero-extends from memory; extsb converts the result to a signed-byte view. Many compilers emit this pair; the recent ISA lba/lbau family is not available on the Xenon, so this two-instruction sequence is the canonical pattern.
• Rc=1 updates CR0 from the full 64-bit signed value — Canary truncates to 32 bits in f.UpdateCR(0, v). For extsb. this is harmless: the result is sign-extended from 8 bits, so the low 32 bits already encode its sign and zero-ness.
• Operand convention is the X-form one (RA destination, RS source). Same as the rest of the logical family.
• No XER side effects.
• RB field unused. Set to 0 by assemblers; ignored on decode.
• Aliasing is fine. extsb r3, r3 rewrites r3 in place.

Related Instructions

• extshx — sign-extend half-word (16 bits).
• extswx — sign-extend word (32 bits).
• rlwinmx, rldiclx — for zero-extending or extracting non-byte-aligned fields.
• lbz, lha (memory ops, outside this page set) — pair with this for signed byte loads.

IBM Reference

• AIX 7.3 — extsb (Extend Sign Byte)