Sylpheed/tools/ppc-manual/alu/mulldx.md

mulldx — Multiply Low Doubleword

Category: Integer ALU · Form: XO · Opcode: 0x7c0001d2

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mulld	mulldx	—	Multiply Low Doubleword
mulldo	mulldx	OE=1	Multiply Low Doubleword
mulld.	mulldx	Rc=1	Multiply Low Doubleword
mulldo.	mulldx	OE=1, Rc=1	Multiply Low Doubleword

Syntax

mulld[OE][Rc] [RD], [RA], [RB]

Encoding

mulldx — form XO

• Opcode word: 0x7c0001d2
• Primary opcode (bits 0–5): 31
• Extended opcode: 233
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	mulldx: read	Source GPR (r0–r31).
RB	mulldx: read	Source GPR.
RD	mulldx: write	Destination GPR.
CR	mulldx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
OE	mulldx: write (conditional)	Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow.

Register Effects

mulldx

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): CR, OE

Status-Register Effects

• mulldx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, when OE=1.

Operation (pseudocode)

RT <- ((RA) * (RB))[64:127]               ; low 64 of signed 64×64

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mulldx

• Canary XML: tools/ppc-instructions.xml — search for mnem="mulldx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:368
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:192
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:987

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_mulldx(PPCHIRBuilder& f, const InstrData& i) {
  // RT <- ((RA) × (RB))[64:127]
  if (i.XO.OE) {
    // With XER update.
    XEINSTRNOTIMPLEMENTED();
  }
  Value* v = f.Mul(f.LoadGPR(i.XO.RA), f.LoadGPR(i.XO.RB));
  f.StoreGPR(i.XO.RT, v);
  if (i.XO.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• Returns the low 64 bits of a signed 64×64 product. Equivalent to (int64_t)(RA * RB) modulo 2^64. Both operands are full 64-bit signed; no truncation on input.
• High bits silently lost. The high 64 bits of the true product are discarded; pair with mulhdx (signed) or mulhdux (unsigned) to recover them.
• OE=1 should set XER[OV] when the 128-bit signed product cannot be represented in 64 bits — i.e. when mulhd RA, RB is not the sign-extension of mulld RA, RB. Canary's OE branch is XEINSTRNOTIMPLEMENTED().
• Rc=1 CR0 update is 32-bit in Canary. f.UpdateCR(0, v) truncates the 64-bit product to INT32, so mulld. gives a CR0 that differs from spec whenever the high 32 bits decide the sign, or the low word is zero while the high word is not.
• Same instruction for signed and unsigned low halves. Modular arithmetic is identical; only the high half (mulhd vs mulhdu) distinguishes the interpretations.
• Multi-cycle latency — slowest of the ALU pipelines after divide.

Related Instructions

• mulhdx, mulhdux — signed/unsigned high halves of the same multiply.
• mullwx — 32-bit signed multiply (low 64).
• mulli — D-form: RT ← (RA[32:63]) × SIMM.
• divdx, divdux — 64-bit divide, often paired with mulld for remainders.

IBM Reference

• AIX 7.3 — mulld (Multiply Low Doubleword)