Sylpheed/tools/ppc-manual/fpu/fnabsx.md

fnabsx — Floating Negative Absolute Value

Category: Floating-Point · Form: X · Opcode: 0xfc000110

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fnabs	fnabsx	—	Floating Negative Absolute Value
fnabs.	fnabsx	Rc=1	Floating Negative Absolute Value

Syntax

fnabs[Rc] [FD], [FB]

Encoding

fnabsx — form X

• Opcode word: 0xfc000110
• Primary opcode (bits 0–5): 63
• Extended opcode: 136
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FB	fnabsx: read	Source B floating-point register.
FD	fnabsx: write	Destination floating-point register.
CR	fnabsx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

fnabsx

• Reads (always): FB
• Reads (conditional): none
• Writes (always): FD
• Writes (conditional): CR

Status-Register Effects

• fnabsx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

FRT <- set_sign(FRB)

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fnabsx

• Canary XML: tools/ppc-instructions.xml — search for mnem="fnabsx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:504
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:83
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:1023

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_fnabsx(PPCHIRBuilder& f, const InstrData& i) {
  // frD <- !abs(frB)
  Value* v = f.Neg(f.Abs(f.LoadFPR(i.X.RB)));
  f.StoreFPR(i.X.RT, v);
  // f.UpdateFPSCR(v, i.X.Rc);
  if (i.X.Rc) {
    // todo
  }
  return 0;
}

Special Cases & Edge Conditions

• Bit-pattern operation, no rounding. fnabs sets the sign bit (bit 0) of the source binary64 value to 1, producing -|FRB|. No precision change, no exception bits. Canary emits Neg(Abs(b)) — vandpd clears the sign bit, then vxorpd sets it. ⚠️ Its Rc=1 branch is empty, so fnabs. does not update CR1 in Canary.
• NaN handling. Returns the source NaN with the sign bit set to 1; payload preserved; signalling/quiet bit unchanged. FPSCR[VXSNAN] is not raised.
• Special values. fnabs(±0) = -0; fnabs(±∞) = -∞; fnabs(±NaN) = -NaN (sign set, payload preserved).
• FPSCR. Hardware does not update FPRF and does not raise any exception bit. Sign-bit ops are not arithmetic.
• Rc=1 (fnabs.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• No FRA. X-form, primary 63, XO 136. Reads FRB only.
• Use case. Less common than fabs/fneg. Useful for unconditional negative-magnitude values, e.g. forcing a value to be on the negative side of zero before a subsequent compare or for bit-pattern setup.

Related Instructions

• fabsx — clear sign bit (positive).
• fnegx — toggle sign bit.
• fmrx — plain register copy.
• fselx — branch-free select; with fabs/fnabs synthesises copysign-like helpers.

IBM Reference

• AIX 7.3 — fnabs (Floating Negative Absolute Value)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor.