Sylpheed/tools/ppc-manual/memory/lwa.md

lwa — Load Word Algebraic

Category: Memory · Form: DS · Opcode: 0xe8000002

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lwa	lwa	—	Load Word Algebraic
lwaux	lwaux	—	Load Word Algebraic with Update Indexed
lwax	lwax	—	Load Word Algebraic Indexed

Syntax

lwa [RD], [ds]([RA0])
lwaux [RD], [RA], [RB]
lwax [RD], [RA0], [RB]

Encoding

lwa — form DS

• Opcode word: 0xe8000002
• Primary opcode (bits 0–5): 58
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS)
11–15	RA	source GPR (0 ⇒ literal 0)
16–29	DS	14-bit signed word-scaled displacement
30–31	XO	extended opcode

lwaux — form X

• Opcode word: 0x7c0002ea
• Primary opcode (bits 0–5): 31
• Extended opcode: 373
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

lwax — form X

• Opcode word: 0x7c0002aa
• Primary opcode (bits 0–5): 31
• Extended opcode: 341
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	lwa: read; lwax: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
ds	lwa: read	14-bit signed word-aligned displacement (DS << 2).
RD	lwa: write; lwaux: write; lwax: write	Destination GPR.
RA	lwaux: read; lwaux: write	Source GPR (r0–r31).
RB	lwaux: read; lwax: read	Source GPR.

Register Effects

lwa

• Reads (always): RA0, ds
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

lwaux

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD, RA
• Writes (conditional): none

lwax

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

EA <- (RA|0) + EXTS(ds || 0b00)
RT <- SEXT32_to_64(MEM(EA, 4))

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lwa

• Canary XML: tools/ppc-instructions.xml — search for mnem="lwa"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:244
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:157
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:497

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lwa(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + EXTS(D || 00)
  // RT <- EXTS(MEM(EA, 4))
  Value* b;
  if (i.DS.RA == 0) {
    b = f.LoadZeroInt64();
  } else {
    b = f.LoadGPR(i.DS.RA);
  }

  Value* offset = f.LoadConstantInt64(XEEXTS16(i.DS.DS << 2));
  Value* rt =
      f.SignExtend(f.ByteSwap(f.LoadOffset(b, offset, INT32_TYPE)), INT64_TYPE);
  f.StoreGPR(i.DS.RT, rt);
  return 0;
}

lwaux

• Canary XML: tools/ppc-instructions.xml — search for mnem="lwaux"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:265
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:159
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:919

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lwaux(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + (RB)
  // RT <- EXTS(MEM(EA, 4))
  // RA <- EA
  Value* ea = CalculateEA(f, i.X.RA, i.X.RB);
  Value* rt = f.SignExtend(f.ByteSwap(f.Load(ea, INT32_TYPE)), INT64_TYPE);
  f.StoreGPR(i.X.RT, rt);
  StoreEA(f, i.X.RA, ea);
  return 0;
}

lwax

• Canary XML: tools/ppc-instructions.xml — search for mnem="lwax"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:276
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:160
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:915

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lwax(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + (RB)
  // RT <- EXTS(MEM(EA, 4))
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  Value* rt = f.SignExtend(f.ByteSwap(f.Load(ea, INT32_TYPE)), INT64_TYPE);
  f.StoreGPR(i.X.RT, rt);
  return 0;
}

Special Cases & Edge Conditions

• Sign-extending word load (32→64). Reads 4 bytes big-endian, treats them as a signed int32, sign-extends to 64 bits. Canary emits SignExtend(ByteSwap(LoadOffset(…, INT32)), INT64).
• No lwau (D-form-update) in PowerISA. Only lwa (DS-form), lwax (X-form), and lwaux (X-form-update) exist. The D-form-update slot is occupied by something else in the encoding space — to update with a 16-bit immediate you must use a separate addi plus lwa.
• DS-form displacement. Like ld, lwa uses a 14-bit signed displacement scaled by 4 (EXTS(ds || 0b00)). The two encoding bits 30–31 distinguish lwa (XO=10) from ld (XO=00) and ldu (XO=01).
• RA0 semantics. RA = 0 in lwa and lwax selects literal zero. lwaux invokes RA = 0 and RA = RT as invalid forms; Canary performs the load before writing back RA, so an RA = RT collision destroys the loaded value.
• Alignment. Xenon tolerates unaligned 4-byte loads. PowerISA permits but does not require an alignment exception; some implementations may raise one for cache-inhibited storage.
• Use lwa rather than lwz + extsw. When the source type is int32_t, lwa is one fused instruction.
• Common in 64-bit code. Sign-extending 32-bit fields out of structures (e.g. signed file offsets) into 64-bit GPRs uses this family.

Related Instructions

• lwz, lwzu, lwzx, lwzux — zero-extending counterparts.
• ld, ldu, ldx, ldux — 64-bit doubleword loads.
• lha, lhax — 16-bit sign-extending loads.
• lwbrx — byte-reversed word load (zero-extending only).
• stw — corresponding store (no separate "store sign-extended" — narrow stores discard the high bits).

IBM Reference

• AIX 7.3 — lwa (Load Word Algebraic)
• AIX 7.3 — lwax / lwaux