Sylpheed/tools/ppc-manual/vmx/vavgsh.md

vavgsh — Vector Average Signed Half Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000542

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vavgsh	vavgsh	—	Vector Average Signed Half Word

Syntax

vavgsh [VD], [VA], [VB]

Encoding

vavgsh — form VX

• Opcode word: 0x10000542
• Primary opcode (bits 0–5): 4
• Extended opcode: 1346
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vavgsh: read	Source A vector register.
VB	vavgsh: read	Source B vector register.
VD	vavgsh: write	Destination vector register.

Register Effects

vavgsh

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vavgsh

• Canary XML: tools/ppc-instructions.xml — search for mnem="vavgsh"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:450
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:312
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:650

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vavgsh(PPCHIRBuilder& f, const InstrData& i) {
  Value* v =
      f.VectorAverage(f.LoadVR(i.VX.VA), f.LoadVR(i.VX.VB), INT16_TYPE, 0);
  f.StoreVR(i.VX.VD, v);
  return 0;
}

Special Cases & Edge Conditions

• Eight signed-half rounding averages. Each VD[i] = (VA[i] + VB[i] + 1) >> 1, computed in 32-bit arithmetic to avoid overflow on the intermediate sum, then truncated back to int16. Rounding is half-up toward +∞.
• Big-endian half lanes. Lane 0 (VD[0..1] after stvx) is the most-significant half.
• No VSCR[SAT] impact. The result is always representable in int16. Canary's x64 backend computes each lane in a scalar loop as (a + b + 1) >> 1 on sign-extended 32-bit values.
• No XER side effects.
• Common usage. Audio sample interpolation, fixed-point Q15 midpoint filters, video upscaling at 16-bit precision.
• Aliasing legal. vavgsh v3, v3, v4 collapses two half-precision streams into one.
• No VMX128 sibling.

Related Instructions

• vavguh — same width, unsigned rounding average.
• vavgsb, vavgsw — signed rounding average at byte / word width.
• vadduhm, vaddshs — addition variants without the divide step.
• vsubuhm — modulo subtract; difference computation before averaging.

IBM Reference

• AIX 7.3 — vavgsh (Vector Average Signed Half Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Average Instructions