Sylpheed/tools/ppc-manual/vmx/vlogefp.md

vlogefp — Vector Log2 Estimate Floating Point

Category: VMX (Altivec) · Form: VX · Opcode: 0x100001ca

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vlogefp	vlogefp	—	Vector Log2 Estimate Floating Point
vlogefp128	vlogefp128	—	Vector128 Log2 Estimate Floating Point

Syntax

vlogefp [VD], [VB]
vlogefp128 [VD], [VB]

Encoding

vlogefp — form VX

• Opcode word: 0x100001ca
• Primary opcode (bits 0–5): 4
• Extended opcode: 458
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vlogefp128 — form VX128_3

• Opcode word: 0x180006f0
• Primary opcode (bits 0–5): 6
• Extended opcode: 1776
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (6)
6–10	VD128l	destination low 5 bits
11–15	IMM	5-bit immediate
16–20	VB128l	source B low 5 bits
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VB	vlogefp: read; vlogefp128: read	Source B vector register.
VD	vlogefp: write; vlogefp128: write	Destination vector register.

Register Effects

vlogefp

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vlogefp128

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vlogefp

• Canary XML: tools/ppc-instructions.xml — search for mnem="vlogefp"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:779
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:345
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:588

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vlogefp(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vlogefp_(f, i.VX.VD, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:773) ──
int InstrEmit_vlogefp_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) {
  // (VD) <- log2(VB)
  Value* v = f.Log2(f.LoadVR(vb));
  f.StoreVR(vd, v);
  return 0;
}

vlogefp128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vlogefp128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:782
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:346
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:782

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vlogefp128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vlogefp_(f, VX128_3_VD128, VX128_3_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:773) ──
int InstrEmit_vlogefp_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) {
  // (VD) <- log2(VB)
  Value* v = f.Log2(f.LoadVR(vb));
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

• Per-lane base-2 logarithm. Each of the four word lanes computes VD[i] = log2(VB[i]) in binary32. Note: the IBM manual specifies a low-precision estimate (≤ 1/32 ULP relative error). Canary calls the host's std::log2 per lane, which is full-precision; hardware-precise programs may observe small numerical differences.
• Use vexptefp for the inverse. Pair gives 2^(log2(x)) ≈ x for positive finite x.
• Big-endian word lanes. Lane 0 is the most-significant word.
• NaN, negatives, zero, ±∞. log2(negative) and log2(NaN) produce NaN; log2(+0) = -∞; log2(-0) = -∞ (per IEEE-754); log2(+∞) = +∞. None of these stickies VSCR[SAT] — float ops never touch SAT.
• No exception, no VSCR[SAT] change, no XER change.
• VMX128 sibling (vlogefp128). Identical semantics with the extended encoding.
• Natural log via change-of-base. ln(x) = log2(x) * (1 / log2(e)) — multiply by a constant with vmaddfp.

Related Instructions

• vexptefp — base-2 exponent (the inverse).
• vrefp — reciprocal estimate.
• vrsqrtefp — reciprocal-square-root estimate.
• vmaddfp — fused multiply-add for change-of-base scaling.

IBM Reference

• AIX 7.3 — vlogefp (Vector log2 Estimate Floating Point)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Estimate Instructions