Sylpheed/tools/ppc-manual/vmx/vmrglw.md

vmrglw — Vector Merge Low Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000018c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmrglw	vmrglw	—	Vector Merge Low Word
vmrglw128	vmrglw128	—	Vector128 Merge Low Word

Syntax

vmrglw [VD], [VA], [VB]
vmrglw128 [VD], [VA], [VB]

Encoding

vmrglw — form VX

• Opcode word: 0x1000018c
• Primary opcode (bits 0–5): 4
• Extended opcode: 396
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vmrglw128 — form VX128

• Opcode word: 0x18000340
• Primary opcode (bits 0–5): 6
• Extended opcode: 832
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vmrglw: read; vmrglw128: read	Source A vector register.
VB	vmrglw: read; vmrglw128: read	Source B vector register.
VD	vmrglw: write; vmrglw128: write	Destination vector register.

Register Effects

vmrglw

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vmrglw128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmrglw

• Canary XML: tools/ppc-instructions.xml — search for mnem="vmrglw"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1017
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:375
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:585

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vmrglw(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vmrglw_(f, i.VX.VD, i.VX.VA, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1006) ──
int InstrEmit_vmrglw_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // (VD.x) = (VA.z)
  // (VD.y) = (VB.z)
  // (VD.z) = (VA.w)
  // (VD.w) = (VB.w)
  Value* v =
      f.Permute(f.LoadConstantUint32(MakePermuteMask(0, 2, 1, 2, 0, 3, 1, 3)),
                f.LoadVR(va), f.LoadVR(vb), INT32_TYPE);
  f.StoreVR(vd, v);
  return 0;
}

vmrglw128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vmrglw128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1020
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:376
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:814

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vmrglw128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vmrglw_(f, VX128_VD128, VX128_VA128, VX128_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1006) ──
int InstrEmit_vmrglw_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // (VD.x) = (VA.z)
  // (VD.y) = (VB.z)
  // (VD.z) = (VA.w)
  // (VD.w) = (VB.w)
  Value* v =
      f.Permute(f.LoadConstantUint32(MakePermuteMask(0, 2, 1, 2, 0, 3, 1, 3)),
                f.LoadVR(va), f.LoadVR(vb), INT32_TYPE);
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

• Interleave the low (least-significant) two words of two vectors: VD = {VA[2], VB[2], VA[3], VB[3]}. Lane 0 is the most-significant word.
• Pairs with vmrghw to cover the four words of each source. Two-instruction word-level transpose.
• Common usage. Bottom half of a 4×4 packed-float matrix transpose; second-half RGBA pixel re-pack after a vmrghw.
• No VSCR interaction, no XER, no exceptions. Pure permute.
• Aliasing legal.
• VMX128 sibling (vmrglw128). Identical semantics with the extended encoding; Canary routes both to one body (InstrEmit_vmrglw_).

Related Instructions

• vmrghw — the "high half" mirror.
• vmrglb, vmrglh — low-half merge at byte / half width.
• vperm, vsldoi — programmable / static permute primitives.
• vspltw — broadcast a single word for blending tasks.

IBM Reference

• AIX 7.3 — vmrglw (Vector Merge Low Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute / Merge