Sylpheed/tools/ppc-manual/vmx/vspltisb.md

vspltisb — Vector Splat Immediate Signed Byte

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000030c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vspltisb	vspltisb	—	Vector Splat Immediate Signed Byte

Syntax

vspltisb [VD], [SIMM]

Encoding

vspltisb — form VX

• Opcode word: 0x1000030c
• Primary opcode (bits 0–5): 4
• Extended opcode: 780
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
SIMM	vspltisb: read	16-bit signed immediate. Sign-extended to 64 bits before use.
VD	vspltisb: write	Destination vector register.

Register Effects

vspltisb

• Reads (always): SIMM
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vspltisb

• Canary XML: tools/ppc-instructions.xml — search for mnem="vspltisb"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1522
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:451
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:618

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vspltisb(PPCHIRBuilder& f, const InstrData& i) {
  // (VD.xyzw) <- sign_extend(uimm)
  Value* v;
  if (i.VX.VA) {
    // Sign extend from 5bits -> 8 and load.
    int8_t simm = (i.VX.VA & 0x10) ? (i.VX.VA | 0xF0) : i.VX.VA;
    v = f.Splat(f.LoadConstantInt8(simm), VEC128_TYPE);
  } else {
    // Zero out the register.
    v = f.LoadZeroVec128();
  }
  f.StoreVR(i.VX.VD, v);
  return 0;
}

Special Cases & Edge Conditions

• Splat a 5-bit signed immediate across all 16 byte lanes. The SIMM field (bits 11–15) is sign-extended from 5 bits to 8 — so the representable range is [−16, +15]. Values 0x10..0x1F decode as negative (−16..−1).
• Constant-generation primitive. vspltisb vD, 0 is the canonical "all-bytes-zero" vector (same net effect as vxor vD, vD, vD). vspltisb vD, -1 is the all-ones mask. vspltisb vD, 1 broadcasts {1, 1, …, 1} for vector-increment tricks.
• No source register. The op doesn't read VA / VB; this saves a register-file read port and keeps constant-generation cheap.
• Big-endian lane order (all lanes identical anyway).
• No flags, no VSCR.
• No VMX128 sibling. Xenon uses the same encoding.

Related Instructions

• vspltish, vspltisw — half-word and word immediate splats (still sign-extended from 5 bits).
• vspltb, vsplth, vspltw — register-indexed splats.
• vxor — alternative "zero vector" idiom when vD is already known.

IBM Reference

• AIX 7.3 — vspltisb (Vector Splat Immediate Signed Byte)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting