Sylpheed/tools/ppc-manual/vmx/vsr.md

vsr — Vector Shift Right

Category: VMX (Altivec) · Form: VX · Opcode: 0x100002c4

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vsr	vsr	—	Vector Shift Right

Syntax

vsr [VD], [VA], [VB]

Encoding

vsr — form VX

• Opcode word: 0x100002c4
• Primary opcode (bits 0–5): 4
• Extended opcode: 708
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vsr: read	Source A vector register.
VB	vsr: read	Source B vector register.
VD	vsr: write	Destination vector register.

Register Effects

vsr

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vsr

• Canary XML: tools/ppc-instructions.xml — search for mnem="vsr"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1573
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:457
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:610

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vsr(PPCHIRBuilder& f, const InstrData& i) {
  Value* va = f.LoadVR(i.VX.VA);
  Value* vb = f.LoadVR(i.VX.VB);

  AssertShiftElementsOk(f, vb);

  Value* v =
      f.Shr(va, f.And(f.Extract(vb, 15, INT8_TYPE), f.LoadConstantInt8(0b111)));
  f.StoreVR(i.VX.VD, v);
  return 0;
}

Special Cases & Edge Conditions

• Whole-register bit shift-right. The 128-bit value VA is shifted right (toward the LSB end) by N bits, where N = VB.b[15] & 7 — the low 3 bits of the last byte of VB. Bits shifted out the bottom are discarded; zero-fill on the top.
• Shift count constraint. The ISA mandates the same 3-bit count across all of VB; Canary reads only byte 15. Splat the count before use.
• Pair with vsro for up to 127-bit shifts. vsro contributes the byte-granular component; vsr the 0..7 residual bits.
• Big-endian. "Right" means toward the LSB end (VD.b[15]).
• No flags, no VSCR.
• No VMX128 sibling.

Related Instructions

• vsro — whole-register shift-right by octets.
• vsl, vslo — left-shift counterparts.
• vsldoi — static-immediate byte shift of VA ‖ VB.
• vsrb, vsrh, vsrw — per-lane logical shifts.

IBM Reference

• AIX 7.3 — vsr (Vector Shift Right)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Shift / Rotate