Files

sim 9bfe96e44d fix(ppc-manual): 543 dead links, from two generator bugs and wrong relative paths

- Category pages linked each family as `<slug>.md`, relative to categories/,
  where no family page lives. They now link `../<category>/<slug>.md`.
- Form pages linked a member into its *own* category directory, so every
  VMX128 sibling (`vsldoi128`) pointed at vmx128/ although its family page is
  under vmx/. They now link into the family's directory.
- Hand-written "Related" and sibling mentions linked other categories' pages
  as if they were in the same directory. 109 are retargeted through the page
  index; 29 that pointed a family page at itself (`vrefp128` on vrefp.md) and
  6 naming instructions the manual has no page for are plain text now.

Regenerated at the existing Canary pin (f21ebd49e): upstream has moved on, and
re-pinning belongs in its own change. The generator reports 0 family pages
changed and is idempotent; the only dead links left are TEMPLATE.md's
placeholders.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>

2026-09-16 22:37:12 +02:00

6.8 KiB

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`vsraw` — Vector Shift Right Algebraic Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000384

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
`vsraw`	`vsraw`	—	Vector Shift Right Algebraic Word
`vsraw128`	`vsraw128`	—	Vector128 Shift Right Arithmetic Word

Syntax

vsraw [VD], [VA], [VB]
vsraw128 [VD], [VA], [VB]

Encoding

`vsraw` — form `VX`

Opcode word: 0x10000384
Primary opcode (bits 0–5): 4
Extended opcode: 900
Synchronising: no

Bits	Field	Meaning
0–5	`OPCD`	primary opcode (4)
6–10	`VRT/VD`	destination vector register
11–15	`VRA/VA`	source A vector register
16–20	`VRB/VB`	source B vector register
21–31	`XO`	extended opcode (11 bits)

`vsraw128` — form `VX128`

Opcode word: 0x18000150
Primary opcode (bits 0–5): 6
Extended opcode: 336
Synchronising: no

Bits	Field	Meaning
0–5	`OPCD`	primary opcode (4 or 5)
6–10	`VD128l`	destination low 5 bits
11–15	`VA128l`	source A low 5 bits
16–20	`VB128l`	source B low 5 bits
21	`VA128H`	source A high bit
22	`—`	reserved
23–25	`VC`	optional VC / XO sub-field
26	`VA128h`	source A middle bit
27	`—`	reserved
28–29	`VD128h`	destination high 2 bits
30–31	`VB128h`	source B high 2 bits

Operands

Field	Role	Description
`VA`	vsraw: read; vsraw128: read	Source A vector register.
`VB`	vsraw: read; vsraw128: read	Source B vector register.
`VD`	vsraw: write; vsraw128: write	Destination vector register.

Register Effects

`vsraw`

Reads (always): VA, VB
Reads (conditional): none
Writes (always): VD
Writes (conditional): none

`vsraw128`

Reads (always): VA, VB
Reads (conditional): none
Writes (always): VD
Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vsraw

Canary XML: tools/ppc-instructions.xml — search for mnem="vsraw"
Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1605
Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:460
Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:629

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vsraw(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vsraw_(f, i.VX.VD, i.VX.VA, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1599) ──
int InstrEmit_vsraw_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // (VD) <- (VA) >>a (VB) by words
  Value* v = f.VectorSha(f.LoadVR(va), f.LoadVR(vb), INT32_TYPE);
  f.StoreVR(vd, v);
  return 0;
}

vsraw128

Canary XML: tools/ppc-instructions.xml — search for mnem="vsraw128"
Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1608
Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:461
Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:809

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vsraw128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vsraw_(f, VX128_VD128, VX128_VA128, VX128_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1599) ──
int InstrEmit_vsraw_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // (VD) <- (VA) >>a (VB) by words
  Value* v = f.VectorSha(f.LoadVR(va), f.LoadVR(vb), INT32_TYPE);
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

Per-lane arithmetic right-shift of signed words. VD.w[i] = (int32)VA.w[i] >> (VB.w[i] & 0x1F) — sign bit propagates. Low 5 bits of each shift-count word are honoured.
Per-lane shift counts. Splat via vspltw / vspltisw for uniform shifts.
Sign extension — distinct from vsrw (zero-fill).
Big-endian word lanes.
No flags, no VSCR.
VMX128 sibling vsraw128.

vsrw — logical-right word.
vslw — word logical-left.
vrlw — word rotate.
vsrab, vsrah — byte / half-word arithmetic-right.

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vsraw — Vector Shift Right Algebraic Word