Files

sim 9bfe96e44d fix(ppc-manual): 543 dead links, from two generator bugs and wrong relative paths

- Category pages linked each family as `<slug>.md`, relative to categories/,
  where no family page lives. They now link `../<category>/<slug>.md`.
- Form pages linked a member into its *own* category directory, so every
  VMX128 sibling (`vsldoi128`) pointed at vmx128/ although its family page is
  under vmx/. They now link into the family's directory.
- Hand-written "Related" and sibling mentions linked other categories' pages
  as if they were in the same directory. 109 are retargeted through the page
  index; 29 that pointed a family page at itself (`vrefp128` on vrefp.md) and
  6 naming instructions the manual has no page for are plain text now.

Regenerated at the existing Canary pin (f21ebd49e): upstream has moved on, and
re-pinning belongs in its own change. The generator reports 0 family pages
changed and is idempotent; the only dead links left are TEMPLATE.md's
placeholders.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>

2026-09-16 22:37:12 +02:00

6.8 KiB

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`vupkhsb` — Vector Unpack High Signed Byte

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000020e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
`vupkhsb`	`vupkhsb`	—	Vector Unpack High Signed Byte
`vupkhsb128`	`vupkhsb128`	—	Vector128 Unpack High Signed Byte

Syntax

vupkhsb [VD], [VB]
vupkhsb128 [VD], [VB]

Encoding

`vupkhsb` — form `VX`

Opcode word: 0x1000020e
Primary opcode (bits 0–5): 4
Extended opcode: 526
Synchronising: no

Bits	Field	Meaning
0–5	`OPCD`	primary opcode (4)
6–10	`VRT/VD`	destination vector register
11–15	`VRA/VA`	source A vector register
16–20	`VRB/VB`	source B vector register
21–31	`XO`	extended opcode (11 bits)

`vupkhsb128` — form `VX128`

Opcode word: 0x18000380
Primary opcode (bits 0–5): 6
Extended opcode: 896
Synchronising: no

Bits	Field	Meaning
0–5	`OPCD`	primary opcode (4 or 5)
6–10	`VD128l`	destination low 5 bits
11–15	`VA128l`	source A low 5 bits
16–20	`VB128l`	source B low 5 bits
21	`VA128H`	source A high bit
22	`—`	reserved
23–25	`VC`	optional VC / XO sub-field
26	`VA128h`	source A middle bit
27	`—`	reserved
28–29	`VD128h`	destination high 2 bits
30–31	`VB128h`	source B high 2 bits

Operands

Field	Role	Description
`VB`	vupkhsb: read; vupkhsb128: read	Source B vector register.
`VD`	vupkhsb: write; vupkhsb128: write	Destination vector register.

Register Effects

`vupkhsb`

Reads (always): VB
Reads (conditional): none
Writes (always): VD
Writes (conditional): none

`vupkhsb128`

Reads (always): VB
Reads (conditional): none
Writes (always): VD
Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vupkhsb

Canary XML: tools/ppc-instructions.xml — search for mnem="vupkhsb"
Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:2041
Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:487
Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:596

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vupkhsb(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vupkhsb_(f, i.VX.VD, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:2032) ──
int InstrEmit_vupkhsb_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) {
  // Vector Unpack High Signed Byte
  // bytes 0-7 expanded to halfwords 0-7 and sign extended
  Value* v =
      f.Unpack(f.LoadVR(vb), PACK_TYPE_TO_HI | PACK_TYPE_8_IN_16 |
                                 PACK_TYPE_IN_SIGNED | PACK_TYPE_OUT_SIGNED);
  f.StoreVR(vd, v);
  return 0;
}

vupkhsb128

Canary XML: tools/ppc-instructions.xml — search for mnem="vupkhsb128"
Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:2044
Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:488
Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:815

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vupkhsb128(PPCHIRBuilder& f, const InstrData& i) {
  uint32_t va = VX128_VA128;
  if (va == 0x60) {
    // Hrm, my instruction tables suck.
    return InstrEmit_vupkhsh_(f, VX128_VD128, VX128_VB128);
  }
  return InstrEmit_vupkhsb_(f, VX128_VD128, VX128_VB128);
}

Special Cases & Edge Conditions

Sign-extend the high 8 of 16 bytes into half-words. VB.b[0..7] are each reinterpreted as int8 and sign-extended to int16 in VD.h[0..7].
Inverse of the high half of vpkshss / vpkshus (within the int8 range — larger int16s cannot survive a round-trip through a saturating pack).
Big-endian lane ordering — VB.b[0] becomes VD.h[0].
No saturation, no flags, no VSCR effect.
VMX128 sibling vupkhsb128.

vupklsb — unpacks the low 8 bytes (same sign-extension).
vupkhsh, vupklsh — half-word → word sign-extending unpacks.
vpkshss, vpkshus — the inverse pack (saturating).
vupkhpx, vupklpx — pixel-format unpacks.

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vupkhsb — Vector Unpack High Signed Byte