Sylpheed/tools/ppc-manual/vmx/vadduhs.md

vadduhs — Vector Add Unsigned Half Word Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000240

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vadduhs	vadduhs	—	Vector Add Unsigned Half Word Saturate

Syntax

vadduhs [VD], [VA], [VB]

Encoding

vadduhs — form VX

• Opcode word: 0x10000240
• Primary opcode (bits 0–5): 4
• Extended opcode: 576
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vadduhs: read	Source A vector register.
VB	vadduhs: read	Source B vector register.
VD	vadduhs: write	Destination vector register.
VSCR	vadduhs: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vadduhs

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vadduhs: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vadduhs

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vadduhs"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:394
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:90
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:482
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3282-3293

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vadduhs => {
            let a = ctx.vr[instr.ra()].as_u16x8();
            let b = ctx.vr[instr.rb()].as_u16x8();
            let mut r = [0u16; 8]; let mut sat = false;
            for i in 0..8 {
                let (v, s) = crate::vmx::sat_add_u16(a[i], b[i]);
                r[i] = v; sat |= s;
            }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u16x8_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Eight unsigned-half lanes, saturating. Each VD[i] = min(VA[i] + VB[i], 0xFFFF) for i = 0..7. Lane 0 (VD[0..1] after stvx) is the most-significant half.
• VSCR[SAT] is sticky-set if any lane clamps. Cleared only by mtvscr. Xenia uses crate::vmx::sat_add_u16 (crates/xenia-cpu/src/vmx.rs) and ORs the per-lane flag.
• One-sided clamp. Unsigned add cannot underflow, so only the upper bound 0xFFFF ever clips.
• The modulo counterpart is vadduhm. Use vadduhs when "too large to fit" must be flagged or clipped — typical for accumulating Q16 unsigned counters.
• No XER side effects.
• Maps directly to _mm_adds_epu16 on SSE2 hosts — semantically identical, including the sticky-saturation observation step (xenia recovers the SAT flag from the per-lane comparison).
• No VMX128 sibling.

Related Instructions

• vadduhm — same width, modulo (non-saturating) add.
• vaddshs — same width, signed saturating add (range -32768..+32767).
• vaddubs, vadduws — unsigned saturating add at byte / word width.
• vsubuhs — the matching unsigned saturating subtract.
• mtvscr / mfvscr — read or clear the sticky VSCR[SAT] bit.

IBM Reference

• AIX 7.3 — vadduhs (Vector Add Unsigned Half Word Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Saturating Integer Arithmetic