Sylpheed/tools/ppc-manual/vmx/vmulesh.md

vmulesh — Vector Multiply Even Signed Half Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000348

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmulesh	vmulesh	—	Vector Multiply Even Signed Half Word

Syntax

vmulesh [VD], [VA], [VB]

Encoding

vmulesh — form VX

• Opcode word: 0x10000348
• Primary opcode (bits 0–5): 4
• Extended opcode: 840
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vmulesh: read	Source A vector register.
VB	vmulesh: read	Source B vector register.
VD	vmulesh: write	Destination vector register.

Register Effects

vmulesh

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmulesh

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vmulesh"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1091
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:108
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:508
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3501-3508

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vmulesh => {
            let a = crate::vmx::as_i16x8(ctx.vr[instr.ra()]);
            let b = crate::vmx::as_i16x8(ctx.vr[instr.rb()]);
            let mut r = [0i32; 4];
            for i in 0..4 { r[i] = a[2 * i] as i32 * b[2 * i] as i32; }
            ctx.vr[instr.rd()] = crate::vmx::from_i32x4(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Even-half signed multiply, word result. Per output word lane:

  VD[i] = int32(int16(VA[2*i]) * int16(VB[2*i]))           ; for i = 0..3
  

  Only the four even-indexed half lanes (lanes 0, 2, 4, 6 in big-endian) are read. Each int16 × int16 product is widened to int32, producing four word results.
• No saturation, no VSCR[SAT]. The full 32-bit product of two signed int16 always fits — even (-32768) * (-32768) = +1_073_741_824 is well within INT32_MAX.
• Pairs with vmulosh (odd-half sibling). Two instructions to cover all eight half lanes.
• Big-endian half indexing. Even half indices 0, 2, 4, 6 correspond to the high-order words of each word slot.
• No XER, no exceptions.
• Aliasing legal.
• No VMX128 sibling.
• Common usage. Q15 × Q15 dot products with full 32-bit precision; signed-half-coefficient FIR taps; first half of a "multiply every half lane" sequence when paired with vmulosh.

Related Instructions

• vmulosh — odd-half sibling (lanes 1, 3, 5, 7).
• vmuleuh, vmulouh — same split, unsigned.
• vmulesb, vmulosb — same family at byte width (→ half-word results).
• vmsumshm, vmsumshs — signed half multiply-sum across pairs (different shape).
• vmladduhm — per-lane modulo multiply-add (low half only).

IBM Reference

• AIX 7.3 — vmulesh (Vector Multiply Even Signed Half Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Multiply Family