Sylpheed/tools/ppc-manual/vmx/vspltw.md

vspltw — Vector Splat Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000028c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vspltw	vspltw	—	Vector Splat Word
vspltw128	vspltw128	—	Vector128 Splat Word

Syntax

vspltw [VD], [VB], [UIMM]
vspltw128 [VD], [VB], [UIMM]

Encoding

vspltw — form VX

• Opcode word: 0x1000028c
• Primary opcode (bits 0–5): 4
• Extended opcode: 652
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vspltw128 — form VX128_3

• Opcode word: 0x18000730
• Primary opcode (bits 0–5): 6
• Extended opcode: 1840
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (6)
6–10	VD128l	destination low 5 bits
11–15	IMM	5-bit immediate
16–20	VB128l	source B low 5 bits
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VB	vspltw: read; vspltw128: read	Source B vector register.
UIMM	vspltw: read; vspltw128: read	16-bit unsigned immediate. Zero-extended.
VD	vspltw: write; vspltw128: write	Destination vector register.

Register Effects

vspltw

• Reads (always): VB, UIMM
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vspltw128

• Reads (always): VB, UIMM
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vspltw

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vspltw"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1529
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:123
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:493
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2328-2334

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vspltw => {
            let uimm = ((instr.raw >> 16) & 0x3) as usize; // UIMM (2 bits for word index)
            let b = ctx.vr[instr.rb()].as_u32x4();
            let val = b[uimm];
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u32x4(val, val, val, val);
            ctx.pc += 4;
        }

vspltw128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vspltw128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1532
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:123
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:668
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2335-2341

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vspltw128 => {
            let uimm = ((instr.raw >> 16) & 0x3) as usize;
            let b = ctx.vr[instr.vb128()].as_u32x4();
            let val = b[uimm];
            ctx.vr[instr.vd128()] = xenia_types::Vec128::from_u32x4(val, val, val, val);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Splat one word across all 4 lanes. UIMM (bits 11–15, low 2 bits honoured) picks which of VB's 4 word lanes is replicated.
• Big-endian index. UIMM = 0 → VB.w[0] (most significant word).
• Typical use: broadcast a float or a 32-bit constant (e.g. splatting a scalar result before feeding it to a per-lane multiply).
• No flags, no VSCR.
• VMX128 sibling vspltw128.
• Compares with vpermwi128: vpermwi128 generalises word splat to any 4-of-4 permutation using an 8-bit immediate (2 bits per output word).

Related Instructions

• vspltb, vsplth — byte / half-word splat siblings.
• vspltisw — immediate splat counterpart.
• vpermwi128 — VMX128 full word permute.
• vperm — byte-granular programmable permute.

IBM Reference

• AIX 7.3 — vspltw (Vector Splat Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting