Sylpheed/tools/ppc-manual/vmx/vsubfp.md

vsubfp — Vector Subtract Floating Point

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000004a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vsubfp	vsubfp	—	Vector Subtract Floating Point
vsubfp128	vsubfp128	—	Vector128 Subtract Floating Point

Syntax

vsubfp [VD], [VA], [VB]
vsubfp128 [VD], [VA], [VB]

Encoding

vsubfp — form VX

• Opcode word: 0x1000004a
• Primary opcode (bits 0–5): 4
• Extended opcode: 74
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vsubfp128 — form VX128

• Opcode word: 0x14000050
• Primary opcode (bits 0–5): 5
• Extended opcode: 80
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vsubfp: read; vsubfp128: read	Source A vector register.
VB	vsubfp: read; vsubfp128: read	Source B vector register.
VD	vsubfp: write; vsubfp128: write	Destination vector register.

Register Effects

vsubfp

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vsubfp128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

for each 32-bit float lane i in 0..3:
    VD[i] <- VA[i] − VB[i]

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vsubfp

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vsubfp"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1686
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:125
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:445
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2012-2024

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vsubfp => {
            // PPCBUG-435.
            let a = ctx.vr[instr.ra()].as_f32x4();
            let b = ctx.vr[instr.rb()].as_f32x4();
            let mut r = [0f32; 4];
            for i in 0..4 {
                let ai = vmx::flush_denorm(a[i]);
                let bi = vmx::flush_denorm(b[i]);
                r[i] = vmx::flush_denorm(ai - bi);
            }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_f32x4_array(r);
            ctx.pc += 4;
        }

vsubfp128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vsubfp128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1689
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:125
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:611
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2025-2037

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vsubfp128 => {
            // PPCBUG-435.
            let a = ctx.vr[instr.va128()].as_f32x4();
            let b = ctx.vr[instr.vb128()].as_f32x4();
            let mut r = [0f32; 4];
            for i in 0..4 {
                let ai = vmx::flush_denorm(a[i]);
                let bi = vmx::flush_denorm(b[i]);
                r[i] = vmx::flush_denorm(ai - bi);
            }
            ctx.vr[instr.vd128()] = xenia_types::Vec128::from_f32x4_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Lane-wise IEEE-754 binary32 subtract. Each of the four lanes computes VD[i] = VA[i] − VB[i], rounded to nearest.
• VSCR[NJ] honoured. Denormals flushed to zero when NJ = 1 (the Xenon boot default).
• NaN propagation. A NaN in either operand propagates to the destination lane.
• ±∞ − ±∞ → NaN. No exception, no VSCR[SAT] set.
• No FPSCR update. VMX float ops are independent of the scalar FPU's status register.
• Big-endian lane indexing.
• VMX128 sibling vsubfp128.
• Aliasing legal. vsubfp v3, v3, v4 is fine.

Related Instructions

• vaddfp — lane-wise float add.
• vmaddfp, vnmsubfp — fused multiply-accumulate variants.
• vmaxfp, vminfp — IEEE-754-aware max/min.
• vcmpeqfp, vcmpgtfp, vcmpgefp, vcmpbfp — compares.

IBM Reference

• AIX 7.3 — vsubfp (Vector Subtract Floating Point)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Arithmetic