Sylpheed/tools/ppc-manual/alu/mulhwx.md

mulhwx — Multiply High Word

Category: Integer ALU · Form: XO · Opcode: 0x7c000096

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mulhw	mulhwx	—	Multiply High Word
mulhw.	mulhwx	Rc=1	Multiply High Word

Syntax

mulhw[Rc] [RD], [RA], [RB]

Encoding

mulhwx — form XO

• Opcode word: 0x7c000096
• Primary opcode (bits 0–5): 31
• Extended opcode: 75
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	mulhwx: read	Source GPR (r0–r31).
RB	mulhwx: read	Source GPR.
RD	mulhwx: write	Destination GPR.
CR	mulhwx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

mulhwx

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): CR

Status-Register Effects

• mulhwx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RT <- high_32_of_signed_multiply((RA)[32:63], (RB)[32:63]) sign-extended to 64

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mulhwx

• Canary XML: tools/ppc-instructions.xml — search for mnem="mulhwx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:326
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:191
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:980

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_mulhwx(PPCHIRBuilder& f, const InstrData& i) {
  // RT[32:64] <- ((RA)[32:63] × (RB)[32:63])[0:31]
  if (i.XO.OE) {
    // With XER update.
    XEINSTRNOTIMPLEMENTED();
  }
  Value* ratrunc =
      f.SignExtend(f.Truncate(f.LoadGPR(i.XO.RA), INT32_TYPE), INT64_TYPE);

  Value* rbtrunc =
      f.SignExtend(f.Truncate(f.LoadGPR(i.XO.RB), INT32_TYPE), INT64_TYPE);

  Value* v = f.Sha(f.Mul(ratrunc, rbtrunc), 32);

  f.StoreGPR(i.XO.RT, v);
  if (i.XO.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• Inputs are the low 32 bits, signed-extended. RA[32:63] and RB[32:63] are sign-extended to 64-bit signed values, multiplied, and the high 32 bits of the 64-bit product are returned in RT[32:63]. The high 32 bits of RT are implementation-defined per spec but xenia masks them to zero (interpreter.rs:222 & 0xFFFF_FFFF).
• Pair with mullwx for the full 64-bit product. Both can issue independently — no fused 32×32→64 instruction.
• No OE bit. Like all mulh* instructions, no overflow flag is produced; the high half is by definition defined.
• Xenia-rs quirk: high 32 bits zeroed. Because spec says they're "undefined", legitimately matching either zero, sign-extension, or garbage. Xenia chooses zero, which differs from the literal Xenon behaviour (which sign-extends in some microarchitecture cases). For game code that doesn't read those bits, the difference is invisible.
• Rc=1 CR0 update. interpreter.rs:225 uses as i32 as i64 — operates on the truncated low 32 bits, which is correct for the defined portion of the result.
• Multi-cycle latency. Multiply is the slowest pipelined ALU op; mulhw shares the divider/multiplier unit.

Related Instructions

• mullwx — low 32 bits of a signed 32×32 product.
• mulhwux — high 32 bits, unsigned interpretation.
• mulhdx, mulhdux, mulldx — 64-bit family.
• divwx — sometimes replaced by reciprocal-mul-then-shift in compiled code.

IBM Reference

• AIX 7.3 — mulhw (Multiply High Word)