Sylpheed/tools/ppc-manual/alu/rldicx.md

rldicx — Rotate Left Doubleword Immediate then Clear

Category: Integer ALU · Form: MD · Opcode: 0x78000008

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
rldic	rldicx	—	Rotate Left Doubleword Immediate then Clear
rldic.	rldicx	Rc=1	Rotate Left Doubleword Immediate then Clear

Syntax

rldic[Rc] [RA], [RS], [SH], [MB]

Encoding

rldicx — form MD

• Opcode word: 0x78000008
• Primary opcode (bits 0–5): 30
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (30)
6–10	RS	source GPR
11–15	RA	destination GPR
16–20	sh	shift amount low 5 bits
21–26	mb/me	6-bit mask field (swapped halves)
27–29	XO	extended opcode
30	sh5	shift amount high bit
31	Rc	record-form flag

Operands

Field	Role	Description
RS	rldicx: read	Source GPR (alias for RD in some stores).
SH	rldicx: read	Shift amount.
MB	rldicx: read	Mask begin bit.
RA	rldicx: write	Source GPR (r0–r31).
CR	rldicx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

rldicx

• Reads (always): RS, SH, MB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• rldicx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

rldicx

• Canary XML: tools/ppc-instructions.xml — search for mnem="rldicx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:906
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:208
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:845

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_rldicx(PPCHIRBuilder& f, const InstrData& i) {
  // n <- sh[5] || sh[0:4]
  // r <- ROTL64(RS, n)
  // b <- mb[5] || mb[0:4]
  // m <- MASK(b, ~n)
  // RA <- r & m
  // TODO: Check if this makes any sense. It works in 535507D4,
  //   but it's the only title I could find that uses this instruction.
  uint32_t sh = (i.MD.SH5 << 5) | i.MD.SH;
  uint32_t mb = (i.MD.MB5 << 5) | i.MD.MB;
  uint64_t m = XEMASK(mb, ~sh);
  Value* v = f.LoadGPR(i.MD.RT);
  if (sh) {
    v = f.RotateLeft(v, f.LoadConstantInt8(sh));
  }
  v = f.And(v, f.LoadConstantUint64(m));
  f.StoreGPR(i.MD.RA, v);
  if (i.MD.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• RA ← ROTL64(RS, SH) & MASK(MB, 63 - SH). Rotate RS left by SH bits, then mask off both ends: clear bits 0..MB-1 and clear bits 64-SH..63. This is the "clear at both edges" variant — useful for inserting a field into an otherwise-zero register.
• SH is a 6-bit immediate spanning bits 16–20 plus bit 30 of the instruction word. Xenia uses the helper instr.sh64() (interpreter.rs:566) to assemble the 6 bits.
• MB is also 6-bit, split-encoded like the rest of the rld* family: (instr.mb() << 1) | ((raw >> 1) & 1).
• Mask is computed as MASK_LEFT(MB) AND MASK_RIGHT(63 - SH). This produces the equivalent of "left-shift RS by SH then clear high bits above bit MB" — a common pattern when MB ≤ 63 - SH.
• Equivalent to a logical shift when MB = 0. rldic RA, RS, SH, 0 ≡ sldi RA, RS, SH (an alias the assembler may prefer).
• Rc=1 CR0 is correctly 64-bit. interpreter.rs:571 uses as i64 directly.
• No XER effect.

Related Instructions

• rldiclx, rldicrx — clear-only-one-side variants.
• rldclx, rldcrx — register-shift forms.
• rldimix — insert under mask.
• rlwinmx — 32-bit cousin.
• sldi (simplified) — rldic RA, RS, n, 0; assemblers prefer this for plain logical left shifts.

IBM Reference

• AIX 7.3 — rldic (Rotate Left Doubleword Immediate then Clear)