7f8a81b8f8
The generator had not been able to run correctly since the manual moved into
`tools/ppc-manual/`: it computed the repository root as `HERE.parent.parent`,
which now names `tools/`, so the XML, Canary's emitters and xenia-rs all stopped
resolving — silently, because both scrapers skipped what they could not find.
Every page's references had been pointing at paths that exist nowhere.
What each source contributed, measured on the 350 pages before this change:
Operation (pseudocode) 251 pages: fixed boilerplate "derives from the xenia-rs
interpreter"; 99 carry real hand-written seeds
C translation 337 pages: the same kind of boilerplate
xenia-rs snapshot 336 pages: the interpreter arm, pasted in — the only
per-instruction semantics on unseeded pages
links xenia-rs opcode/decoder/interpreter + Canary emitter
Now:
* semantics come from **Xenia Canary**, the reference emulator, read through
`git show` at a pinned upstream commit (`origin/canary_experimental`,
f21ebd49e9). Not our checkout: it carries instrumentation and lacked
upstream's `mcrf` fix, so it would have published probes and a wrong `mcrf`.
Each page embeds the emitter (`InstrEmit_<mnem>`), and for the 128 pure
one-line delegations also the helper that holds the semantics.
* decode references point at `crates/sylpheed-ppc` — the decoder that
produces `sylpheed.db` — as in-repo relative links.
* the boilerplate now says what is true, and the C translation guide maps
Canary's actual HIR calls, checked against `ppc_hir_builder.h` (including
that `UpdateCR(n, v)` truncates to 32 bits).
* `rust_scraper.py` -> `decoder_scraper.py` (interpreter half dropped);
missing sources are now errors, not empty results.
Verified:
consistency checks 455 XML entries, 350 families, 598 index keys
hand-written tails 386/386 byte-identical after regeneration
xenia-rs in generated 0
pages with a snapshot 349/350 (was 336) — `dcbi` has no Canary emitter at all
in-repo decoder links 910/910 resolve to a line holding the identifier
emitter boundaries brace counter == column-0 `}` rule on 521/521;
preprocessor model unit-tested (#if 0/#else/#elif)
idempotency re-run: 0 pages updated, 0 working-tree changes
Hand-written notes (outside the generated regions) are not rewritten here:
* 110 links into `../../xenia-rs/...` were dead; they now point at the file in
the archived repository (git.mc02.dev/fabi/xenia-rs @ 8401d4d). Line anchors
were dropped because the notes predate that commit — 0 of 441 old line
ranges match it — and a precise-looking wrong anchor is worse than none. The
link text, which carries the author's line numbers, is unchanged.
* 140 prose claims about xenia-rs's behaviour remain. 23 are verified to hold
for Canary too (the 32-bit CR0 truncation, OE left unimplemented); the other
114 need checking one by one, and some invert — e.g. `divdx` notes a correct
64-bit CR0 update in xenia-rs where Canary's `UpdateCR` truncates. Left for
a deliberate pass rather than a blind substitution.
Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
4.3 KiB
4.3 KiB
xoris — XOR Immediate Shifted
Category: Integer ALU · Form: D · Opcode:
0x6c000000
Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
|---|---|---|---|
xoris |
xoris |
— | XOR Immediate Shifted |
Syntax
xoris [RA], [RS], [UIMM]
Encoding
xoris — form D
- Opcode word:
0x6c000000 - Primary opcode (bits 0–5):
27 - Extended opcode: —
- Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode |
| 6–10 | RT |
destination GPR (or RS when storing) |
| 11–15 | RA |
source GPR (0 ⇒ literal 0 for RA0 forms) |
| 16–31 | D/SI/UI |
16-bit signed or unsigned immediate |
Operands
| Field | Role | Description |
|---|---|---|
RS |
xoris: read | Source GPR (alias for RD in some stores). |
UIMM |
xoris: read | 16-bit unsigned immediate. Zero-extended. |
RA |
xoris: write | Source GPR (r0–r31). |
Register Effects
xoris
- Reads (always):
RS,UIMM - Reads (conditional): none
- Writes (always):
RA - Writes (conditional): none
Status-Register Effects
No condition-register or status-register effects.
Operation (pseudocode)
RA <- (RS) ^ (UIMM || 0x0000)
C Translation Example
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
Implementation References
xoris
- Canary XML:
tools/ppc-instructions.xml— search formnem="xoris" - Canary emitter:
src/xenia/cpu/ppc/ppc_emit_alu.cc:846 - Sylpheed opcode:
crates/sylpheed-ppc/src/opcode.rs:498 - Sylpheed decoder:
crates/sylpheed-ppc/src/decoder.rs:465
Canary emitter (frozen snapshot @ f21ebd49e9)
int InstrEmit_xoris(PPCHIRBuilder& f, const InstrData& i) {
// RA <- (RS) XOR (i32.0 || UI || i16.0)
Value* ra =
f.Xor(f.LoadGPR(i.D.RT), f.LoadConstantUint64(XEEXTZ16(i.D.DS) << 16));
f.StoreGPR(i.D.RA, ra);
return 0;
}
Special Cases & Edge Conditions
- No record form. Like all immediate logicals other than
andi./andis.,xorisdoes not update CR0. - Immediate is zero-extended then shifted left 16. Only bits 32–47 of
RA(PowerISA bit numbering) can be flipped; the high 32 bits and low 16 bits ofRAcome fromRSunchanged. - Common pattern with
xorito flip arbitrary 32-bit bitmasks:xoris RA, RS, hi16; xori RA, RA, lo16. - 64-bit operation.
interpreter.rs:342. - No
XER, noCR. RA = 0readsr0(not literal zero).- Used to toggle the high half of a 32-bit word, e.g.
xoris r3, r3, 0x8000flips bit 32 (the sign bit of the low word) — a one-instruction sign-flip on a 32-bit value.
Related Instructions
xori— companion (immediate not shifted).xorx— register-register XOR.oris,andisx— sister immediate-shifted logicals.