Sylpheed/tools/ppc-manual/control/mtfsfix.md

mtfsfix — Move to FPSCR Field Immediate

Category: Control / CR / SPR · Form: X · Opcode: 0xfc00010c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mtfsfi	mtfsfix	—	Move to FPSCR Field Immediate
mtfsfi.	mtfsfix	Rc=1	Move to FPSCR Field Immediate

Syntax

mtfsfi[Rc] [CRFD], [IMM]

Encoding

mtfsfix — form X

• Opcode word: 0xfc00010c
• Primary opcode (bits 0–5): 63
• Extended opcode: 134
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
IMM	mtfsfix: read	Generic immediate field.
CRFD	mtfsfix: write	CR destination field (crf, 0–7).
CR	mtfsfix: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

mtfsfix

• Reads (always): IMM
• Reads (conditional): none
• Writes (always): CRFD
• Writes (conditional): CR

Status-Register Effects

• mtfsfix: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mtfsfix

• Canary XML: tools/ppc-instructions.xml — search for mnem="mtfsfix"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:452
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:181
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:1022

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_mtfsfix(PPCHIRBuilder& f, const InstrData& i) {
  // FPSCR[crfD] <- IMM

  // Create a mask.
  uint32_t mask = 0xF << (0x1C - (i.X.RT & 0x1C));
  uint32_t value = i.X.RB << (0x1C - (i.X.RT & 0x1C));

  Value* fpscr = f.LoadFPSCR();
  fpscr = f.And(fpscr, f.LoadConstantInt32(~mask));
  fpscr = f.Or(fpscr, f.LoadConstantInt32(value));
  f.StoreFPSCR(fpscr);

  // Update the system rounding mode.
  if (mask & 0x7) {
    f.SetRoundingMode(f.And(fpscr, f.LoadConstantInt32(7)));
  }

  if (i.X.Rc) {
    f.CopyFPSCRToCR1();
  }

  return 0;
}

Special Cases & Edge Conditions

• Operation. Loads a 4-bit immediate (IMM, encoded in instruction bits 16..19) into a single FPSCR field selected by CRFD (3-bit, 0..7). All other FPSCR fields are preserved.
• Most common use: rounding-mode set. mtfsfi 7, 0 selects round-to-nearest, mtfsfi 7, 1 round-toward-zero, mtfsfi 7, 2 round-toward-+∞, mtfsfi 7, 3 round-toward-−∞. The four immediate values map to RN per IEEE-754. Compilers emit this when transitioning into and out of strict-IEEE regions.
• No FPR source. Unlike mtfsfx, mtfsfi doesn't need an FPR — it carries its 4-bit value in the instruction word, making it cheaper for constant updates.
• Rc=1. mtfsfi. copies FPSCR's top 4 bits (FX, FEX, VX, OX) into CR1 after the write.
• Restrictions in newer PowerISA. v2.05+ disallows writing FEX/VX (summary bits) via mtfsfi. xenia-rs does not enforce this — the immediate goes straight into the chosen field.
• xenia simplification. xenia stores FPSCR as a u32 and applies the field-shift correctly. Same caveat as mtfsf: most xenia FP paths don't honour FPSCR, so the rounding-mode change is architecturally visible (via mffsx) but typically does not change subsequent FP results.
• Not synchronising. PowerISA recommends isync after rounding-mode changes if subsequent FP correctness depends on the new mode.

Related Instructions

• mtfsfx — write FPSCR fields from an FPR (uses 8-bit field-mask).
• mtfsb0x, mtfsb1x — clear / set a single FPSCR bit.
• mffsx — read FPSCR.
• mcrfs — FPSCR field → CR field (also clears sticky bits).

mtfsfi is the simplified form (Rc=0); mtfsfi. is the recording variant.

IBM Reference

• AIX 7.3 — mtfsfi (Move to FPSCR Field Immediate)
• PowerISA v2.07B, Book I §4.6.6 — FPSCR-field write semantics and the FEX/VX restriction.