Sylpheed/tools/ppc-manual/fpu/fsubx.md

fsubx — Floating Subtract

Category: Floating-Point · Form: A · Opcode: 0xfc000028

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fsub	fsubx	—	Floating Subtract
fsub.	fsubx	Rc=1	Floating Subtract

Syntax

fsub[Rc] [FD], [FA], [FB]

Encoding

fsubx — form A

• Opcode word: 0xfc000028
• Primary opcode (bits 0–5): 63
• Extended opcode: 20
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (59 or 63)
6–10	FRT	destination FPR
11–15	FRA	source A FPR
16–20	FRB	source B FPR
21–25	FRC	source C FPR (multiplier for madd-style ops)
26–30	XO	extended opcode (5 bits)
31	Rc	record-form flag (updates CR1)

Operands

Field	Role	Description
FA	fsubx: read	Source A floating-point register (fr0–fr31).
FB	fsubx: read	Source B floating-point register.
FD	fsubx: write	Destination floating-point register.
CR	fsubx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fsubx: write	Floating-Point Status and Control Register.

Register Effects

fsubx

• Reads (always): FA, FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fsubx: CR1 ← FPSCR[FX, FEX, VX, OX] when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

FRT <- FRA − FRB

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fsubx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="fsubx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:127
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:30
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:921
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2575-2584

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::fsubx => {
            let a = ctx.fpr[instr.ra()];
            let b = ctx.fpr[instr.rb()];
            fpscr::check_invalid_add(ctx, a, b, true);
            let result = a - b;
            ctx.fpr[instr.rd()] = result;
            fpscr::update_after_op(ctx, result, a.is_finite() && b.is_finite());
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Double precision. fsub operates on IEEE-754 binary64. The single-precision sibling is fsubsx, which rounds the result to binary32 before re-encoding it into the 64-bit FPR.
• ±∞ − ±∞ is the canonical invalid case. Same-signed infinity subtraction (or opposite-signed addition) yields QNaN(VXISI) and sets FPSCR[VXISI, VX, FX].
• FPSCR side effects. Hardware updates FPRF, FR, FI, FX plus exception bits OX, UX, XX, VXISI, VXSNAN as appropriate. xenia-rs's interpreter does not model FPSCR updates — a xenia quirk that almost never matters in practice.
• Rc=1 (fsub.) writes CR1 from FPSCR[FX, FEX, VX, OX].
• NaN propagation. Any NaN operand yields a quiet NaN; a signalling NaN input is quietened (signalling bit cleared) per PowerISA. Host f64 - is relied on for the value.
• Sign of zero. +0 − +0 = +0 in round-to-nearest, −0 in round-toward-negative-infinity. xenia inherits host semantics.
• Denormal flush. Xenon boots with FPSCR[NI]=1 (non-IEEE mode) so subnormal results flush to zero on hardware. Xenia produces IEEE-compliant denormals from the host FPU; titles relying on flush-to-zero typically see no observable difference for game logic but may see subtle differences in audio DSP.
• Encoding. A-form, primary 63, XO 20. FRC is don't-care for sub.

Related Instructions

• fsubsx — single-precision subtract (rounds to binary32).
• faddx, faddsx — add counterparts; subtract is implemented as add-with-negated-B on most cores.
• fnegx — sign flip (the bit-pattern operation behind −FRB).
• fmsubx, fnmsubx — fused multiply-subtract (single rounding step).
• mffsx, mtfsfx, mtfsb0x, mtfsb1x — FPSCR control.

IBM Reference

• AIX 7.3 — fsub (Floating Subtract)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor.