Sylpheed/tools/ppc-manual/memory/lwarx.md

lwarx — Load Word and Reserve Indexed

Category: Memory · Form: X · Opcode: 0x7c000028

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lwarx	lwarx	—	Load Word and Reserve Indexed

Syntax

lwarx [RD], [RA0], [RB]

Encoding

lwarx — form X

• Opcode word: 0x7c000028
• Primary opcode (bits 0–5): 31
• Extended opcode: 20
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	lwarx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	lwarx: read	Source GPR.
RD	lwarx: write	Destination GPR.

Register Effects

lwarx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lwarx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lwarx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:795
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:49
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:754
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1207-1222

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lwarx => {
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
            let val = mem.read_u32(ea);
            ctx.gpr[instr.rd()] = val as u64;
            ctx.reserved_line = ea & !RESERVATION_MASK;
            ctx.reserved_val = val as u64;
            ctx.has_reservation = true;
            ctx.reservation_width = 4; // PPCBUG-151: word reservation
            if let Some(t) = &ctx.reservation_table {
                if t.is_enabled() {
                    ctx.reserved_generation = t.reserve(ea, ctx.hw_id);
                }
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Reservation set on the addressed word. Loads MEM(EA, 4) zero-extended to 64 bits and atomically establishes a reservation on EA. A subsequent stwcx at the same address completes only if the reservation is still valid. Together they form the canonical 32-bit load-linked / store-conditional pair for lock-free updates and futexes.
• One reservation per thread. Xenia's snapshot writes reserved_addr, reserved_val, and has_reservation in the per-context state. Hardware behaves the same: each hardware thread has at most one reservation. A second lwarx (or ldarx) discards the previous reservation.
• Granule. Architecturally one naturally-aligned word; on Xenon the practical reservation granule is one cache line (128 bytes) — any store to that line by another agent invalidates the reservation. Xenia simplifies to per-address tracking, which can let real-hardware-failing pairs succeed under emulation.
• Alignment requirement. EA must be 4-byte aligned. An unaligned lwarx raises an alignment exception on hardware; xenia does not check.
• RA0 semantics. When RA = 0, base is literal zero — lwarx RT, 0, RB reads at exact RB.
• Reservation-loss events. Any exception, context switch, or store by another thread to the reserved line clears the reservation. Application code treats stwcx. failure (CR0[EQ]=0) as a normal retry condition.
• Pair atomically. Code must be lwarx ... do work ... stwcx. with no intervening loads/stores that could reorder. Optionally fence with lwsync inside the loop.

Related Instructions

• stwcx — store-conditional word (the matching half of the pair).
• ldarx / stdcx — 64-bit reservation pair.
• lwz, lwzx — non-reserving word loads.
• sync, lwsync, isync — barriers commonly placed around reservation pairs.

IBM Reference

• AIX 7.3 — lwarx (Load Word and Reserve Indexed)
• PowerISA v2.07B Book II § "Atomic Update Primitives" for the reservation model and granule rules.