Sylpheed/tools/ppc-manual/vmx/vmuloub.md

vmuloub — Vector Multiply Odd Unsigned Byte

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000008

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmuloub	vmuloub	—	Vector Multiply Odd Unsigned Byte

Syntax

vmuloub [VD], [VA], [VB]

Encoding

vmuloub — form VX

• Opcode word: 0x10000008
• Primary opcode (bits 0–5): 4
• Extended opcode: 8
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vmuloub: read	Source A vector register.
VB	vmuloub: read	Source B vector register.
VD	vmuloub: write	Destination vector register.

Register Effects

vmuloub

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmuloub

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vmuloub"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1116
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:109
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:437
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3461-3468

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vmuloub => {
            let a = ctx.vr[instr.ra()].as_bytes();
            let b = ctx.vr[instr.rb()].as_bytes();
            let mut r = [0u16; 8];
            for i in 0..8 { r[i] = a[2 * i + 1] as u16 * b[2 * i + 1] as u16; }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u16x8_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Odd-lane unsigned byte multiply. Only the odd-indexed byte lanes (1, 3, 5, 7, 9, 11, 13, 15 — big-endian) of VA and VB participate. Each 8×8 unsigned product widens to an unsigned 16-bit half-word in the corresponding half-word of VD. Pairing: VD.h[i] = VA.b[2*i+1] * VB.b[2*i+1] for i ∈ 0..7.
• Lane-count reduction. 16 byte lanes → 8 half-word lanes.
• No overflow. 0xFF * 0xFF = 0xFE01 fits in 16 bits. VSCR[SAT] is not touched.
• Pair with vmuleub to get every byte product; re-interleave with vmrghh/vmrglh, or use vmsumubm for a fused multiply-accumulate.
• Unsigned arithmetic. No sign-extension; negatives don't exist for b lanes in this op. Contrast with vmulosb.
• No Rc, no XER. No VMX128 sibling.

Related Instructions

• vmuleub — even-lane unsigned byte twin.
• vmulosb, vmulesb — signed byte even/odd.
• vmulouh, vmuleuh — unsigned half-word even/odd.
• vmsumubm — fused unsigned-byte multiply-sum.
• vmrghh, vmrglh — interleave even/odd half-word products.

IBM Reference

• AIX 7.3 — vmuloub (Vector Multiply Odd Unsigned Byte)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic