Sylpheed/tools/ppc-manual/vmx/vsraw.md

vsraw — Vector Shift Right Algebraic Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000384

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vsraw	vsraw	—	Vector Shift Right Algebraic Word
vsraw128	vsraw128	—	Vector128 Shift Right Arithmetic Word

Syntax

vsraw [VD], [VA], [VB]
vsraw128 [VD], [VA], [VB]

Encoding

vsraw — form VX

• Opcode word: 0x10000384
• Primary opcode (bits 0–5): 4
• Extended opcode: 900
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vsraw128 — form VX128

• Opcode word: 0x18000150
• Primary opcode (bits 0–5): 6
• Extended opcode: 336
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vsraw: read; vsraw128: read	Source A vector register.
VB	vsraw: read; vsraw128: read	Source B vector register.
VD	vsraw: write; vsraw128: write	Destination vector register.

Register Effects

vsraw

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vsraw128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vsraw

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vsraw"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1619
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:124
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:514
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2438-2449

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vsraw | PpcOpcode::vsraw128 => {
            let (va, vb, vd) = vmx_reg_triple(instr);
            let a = ctx.vr[va].as_u32x4();
            let b = ctx.vr[vb].as_u32x4();
            let mut r = [0u32; 4];
            for i in 0..4 {
                let sh = b[i] & 0x1F;
                r[i] = (a[i] as i32 >> sh) as u32;
            }
            ctx.vr[vd] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }

vsraw128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vsraw128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1622
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:124
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:694
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2438-2449

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vsraw | PpcOpcode::vsraw128 => {
            let (va, vb, vd) = vmx_reg_triple(instr);
            let a = ctx.vr[va].as_u32x4();
            let b = ctx.vr[vb].as_u32x4();
            let mut r = [0u32; 4];
            for i in 0..4 {
                let sh = b[i] & 0x1F;
                r[i] = (a[i] as i32 >> sh) as u32;
            }
            ctx.vr[vd] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Per-lane arithmetic right-shift of signed words. VD.w[i] = (int32)VA.w[i] >> (VB.w[i] & 0x1F) — sign bit propagates. Low 5 bits of each shift-count word are honoured.
• Per-lane shift counts. Splat via vspltw / vspltisw for uniform shifts.
• Sign extension — distinct from vsrw (zero-fill).
• Big-endian word lanes.
• No flags, no VSCR.
• VMX128 sibling vsraw128.

Related Instructions

• vsrw — logical-right word.
• vslw — word logical-left.
• vrlw — word rotate.
• vsrab, vsrah — byte / half-word arithmetic-right.

IBM Reference

• AIX 7.3 — vsraw (Vector Shift Right Arithmetic Integer Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Shift / Rotate