Sylpheed/tools/ppc-manual/vmx/vsro.md

vsro — Vector Shift Right Octet

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000044c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vsro	vsro	—	Vector Shift Right Octet
vsro128	vsro128	—	Vector128 Shift Right Octet

Syntax

vsro [VD], [VA], [VB]
vsro128 [VD], [VA], [VB]

Encoding

vsro — form VX

• Opcode word: 0x1000044c
• Primary opcode (bits 0–5): 4
• Extended opcode: 1100
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vsro128 — form VX128

• Opcode word: 0x140003d0
• Primary opcode (bits 0–5): 5
• Extended opcode: 976
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vsro: read; vsro128: read	Source A vector register.
VB	vsro: read; vsro128: read	Source B vector register.
VD	vsro: write; vsro128: write	Destination vector register.

Register Effects

vsro

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vsro128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vsro

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vsro"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1651
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:124
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:528
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3945-3954

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vsro | PpcOpcode::vsro128 => {
            let is_128 = matches!(instr.opcode, PpcOpcode::vsro128);
            let (ra, rb, rd) = if is_128 { (instr.va128(), instr.vb128(), instr.vd128()) }
                               else { (instr.ra(), instr.rb(), instr.rd()) };
            let a = u128::from_be_bytes(ctx.vr[ra].as_bytes());
            let nbytes = ((ctx.vr[rb].as_bytes()[15] >> 3) & 0xF) as u32;
            let r = if nbytes == 0 { a } else { a >> (nbytes * 8) };
            ctx.vr[rd] = xenia_types::Vec128::from_bytes(r.to_be_bytes());
            ctx.pc += 4;
        }

vsro128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vsro128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1654
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:124
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:633
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3945-3954

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vsro | PpcOpcode::vsro128 => {
            let is_128 = matches!(instr.opcode, PpcOpcode::vsro128);
            let (ra, rb, rd) = if is_128 { (instr.va128(), instr.vb128(), instr.vd128()) }
                               else { (instr.ra(), instr.rb(), instr.rd()) };
            let a = u128::from_be_bytes(ctx.vr[ra].as_bytes());
            let nbytes = ((ctx.vr[rb].as_bytes()[15] >> 3) & 0xF) as u32;
            let r = if nbytes == 0 { a } else { a >> (nbytes * 8) };
            ctx.vr[rd] = xenia_types::Vec128::from_bytes(r.to_be_bytes());
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Whole-register shift-right by octets (bytes). VA is shifted right by N bytes, where N = (VB.b[15] >> 3) & 0xF. Top end is zero-filled.
• Shift count constraint. Uniform 4-bit count required across VB; xenia reads only byte 15.
• Pair with vsr for full bit-level shifts. vsro handles bytes; vsr handles the 0..7 residual.
• Big-endian. "Right" = toward LSB end (VD.b[15]).
• No flags, no VSCR.
• VMX128 sibling vsro128.

Related Instructions

• vsr — bit-level whole-register shift-right.
• vslo — shift-left by octet.
• vsldoi — static-immediate variant.
• vsrb, vsrh, vsrw — per-lane logical shifts.

IBM Reference

• AIX 7.3 — vsro (Vector Shift Right by Octet)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Shift / Rotate