Sylpheed/tools/ppc-manual/vmx/vxor.md

vxor — Vector Logical XOR

Category: VMX (Altivec) · Form: VX · Opcode: 0x100004c4

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vxor	vxor	—	Vector Logical XOR
vxor128	vxor128	—	Vector128 Logical XOR

Syntax

vxor [VD], [VA], [VB]
vxor128 [VD], [VA], [VB]

Encoding

vxor — form VX

• Opcode word: 0x100004c4
• Primary opcode (bits 0–5): 4
• Extended opcode: 1220
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vxor128 — form VX128

• Opcode word: 0x14000310
• Primary opcode (bits 0–5): 5
• Extended opcode: 784
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vxor: read; vxor128: read	Source A vector register.
VB	vxor: read; vxor128: read	Source B vector register.
VD	vxor: write; vxor128: write	Destination vector register.

Register Effects

vxor

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vxor128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vxor

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vxor"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:2246
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:130
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:532
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2235-2243

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vxor | PpcOpcode::vxor128 => {
            let (va, vb, vd) = vmx_reg_triple(instr);
            let a = ctx.vr[va].as_u32x4();
            let b = ctx.vr[vb].as_u32x4();
            let mut r = [0u32; 4];
            for i in 0..4 { r[i] = a[i] ^ b[i]; }
            ctx.vr[vd] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }

vxor128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vxor128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:2249
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:130
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:627
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2235-2243

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vxor | PpcOpcode::vxor128 => {
            let (va, vb, vd) = vmx_reg_triple(instr);
            let a = ctx.vr[va].as_u32x4();
            let b = ctx.vr[vb].as_u32x4();
            let mut r = [0u32; 4];
            for i in 0..4 { r[i] = a[i] ^ b[i]; }
            ctx.vr[vd] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Bitwise XOR across the full 128-bit register. Lane-agnostic.
• vxor VD, VD, VD is the canonical "vector zero" idiom. Every Xenon compiler uses this to materialise the all-zero vector; xenia-rs's interpreter does not special-case it (it still reads the register), but the JIT / translator can fold it at emit time.
• Aliasing legal. vxor v3, v3, v4 toggles bits from v4 into v3.
• No flags, no VSCR.
• VMX128 sibling vxor128. Identical semantics; wider register file.
• Compare-then-XOR is the cheapest "mask flip" when vnor is not wanted (e.g. to toggle only certain bits, not every bit).

Related Instructions

• vor, vand, vandc, vnor — the rest of the Altivec boolean primitives.
• vsel — three-input bit-select; equivalent to (VA & ~VC) | (VB & VC).
• vcmpequb, vcmpequh, vcmpequw — produce masks XORed against.

IBM Reference

• AIX 7.3 — vxor (Vector Logical XOR)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 3 — Logical Operations