Sylpheed/tools/ppc-manual/control/mtspr.md

mtspr — Move to Special-Purpose Register

Category: Control / CR / SPR · Form: XFX · Opcode: 0x7c0003a6

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mtspr	mtspr	—	Move to Special-Purpose Register

Syntax

mtspr [SPR], [RS]

Encoding

mtspr — form XFX

• Opcode word: 0x7c0003a6
• Primary opcode (bits 0–5): 31
• Extended opcode: 467
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination / source GPR
11–20	spr/tbr/FXM	SPR/TBR number (byte-swapped halves) or CR field mask
21–30	XO	extended opcode
31	—	reserved

Operands

Field	Role	Description
RS	mtspr: read	Source GPR (alias for RD in some stores).
SPR	mtspr: write	Special-Purpose-Register number. Encoded with the two 5-bit halves swapped (bits 11-15 become the high half, bits 16-20 the low half).

Register Effects

mtspr

• Reads (always): RS
• Reads (conditional): none
• Writes (always): SPR
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

n <- spr_number(SPR)
SPR(n) <- (RS)

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mtspr

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="mtspr"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_control.cc:771
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:55
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:810
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1596-1626

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::mtspr => {
            let spr = instr.spr();
            let val = ctx.gpr[instr.rs()];
            match spr {
                crate::context::spr::XER => ctx.set_xer(val as u32),
                crate::context::spr::LR => ctx.lr = val,
                crate::context::spr::CTR => ctx.ctr = val as u32 as u64,
                crate::context::spr::DEC => ctx.dec = val as u32,
                crate::context::spr::TBL_WRITE => {
                    ctx.timebase = (ctx.timebase & 0xFFFF_FFFF_0000_0000) | (val & 0xFFFF_FFFF);
                }
                crate::context::spr::TBU_WRITE => {
                    ctx.timebase = (ctx.timebase & 0x0000_0000_FFFF_FFFF) | ((val & 0xFFFF_FFFF) << 32);
                }
                crate::context::spr::VRSAVE => ctx.vrsave = val as u32,
                // Benign writes — swallow silently to avoid false Unimplemented
                // warnings on SPRs that have no observable effect in userspace.
                crate::context::spr::SPRG0
                | crate::context::spr::SPRG1
                | crate::context::spr::SPRG2
                | crate::context::spr::SPRG3
                | crate::context::spr::HID0
                | crate::context::spr::HID1
                | crate::context::spr::DAR
                | crate::context::spr::DSISR => {}
                _ => {
                    tracing::warn!("mtspr: unimplemented SPR {}", spr);
                }
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• SPR halves are swapped in the encoding. As with mfspr, the 10-bit spr field stores the two 5-bit halves transposed. Software always names the logical SPR number; assemblers handle the swap. Decoded number n = ((field & 0x1F) << 5) | ((field >> 5) & 0x1F).

• SPRs writable from userspace (Xenon, modelled by xenia).

  Decoded #	Name	Effect
  1	XER	unpacked into ctx.xer_so/xer_ov/xer_ca and length field
  8	LR	ctx.lr ← RS
  9	CTR	ctx.ctr ← RS
  256	VRSAVE	ctx.vrsave ← RS & 0xFFFFFFFF

• SPRs xenia silently swallows (no observable effect). SPRG0..3, HID0, HID1, DAR, DSISR — these are kernel/diagnostic registers; xenia accepts the write to avoid spurious "unimplemented SPR" warnings, but the value is discarded.

• Privileged SPRs. On real hardware, writes to MSR-visible kernel SPRs (SPRG0..3, HID0/1, DSISR, DAR, PIR, etc.) require supervisor mode and trap from problem state. xenia does not enforce privilege.

• Time-base writes are privileged. mtspr 268/269 (TBL/TBU) only works in supervisor mode on real hardware. xenia will warn mtspr: unimplemented SPR for these — do not assume the time base can be guest-written.

• Simplified mnemonics. mtxer RS ≡ mtspr 1, RS, mtlr RS ≡ mtspr 8, RS, mtctr RS ≡ mtspr 9, RS. These dominate Xbox 360 disassembly.

• No CR / XER side effects. mtspr itself doesn't record (the target SPR may itself be XER, in which case XER is being directly overwritten).

• Not synchronising. xenia's XML omits the sync flag; PowerISA does require some mtspr cases (e.g. SDR1, MMU regs) to be context-synchronising — none of them appear in title binaries.

Related Instructions

• mfspr — inverse: read an SPR into a GPR.
• mftb — read time-base (preferred over mfspr TBL/TBU).
• mtmsr, mtmsrd — write MSR (separate opcode).
• mcrxr — sample-and-clear XER's overflow/carry bits.

Simplified Mnemonics

Simplified	Expansion
mtxer RS	mtspr 1, RS
mtlr RS	mtspr 8, RS
mtctr RS	mtspr 9, RS

IBM Reference

• AIX 7.3 — mtspr (Move to Special Purpose Register)
• PowerISA v2.07B, Book III §4 — SPR number table and privilege rules.