Sylpheed/tools/ppc-manual/memory/icbi.md

icbi — Instruction Cache Block Invalidate

Category: Memory · Form: X · Opcode: 0x7c0007ac

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
icbi	icbi	—	Instruction Cache Block Invalidate

Syntax

icbi [RA], [RB]

Encoding

icbi — form X

• Opcode word: 0x7c0007ac
• Primary opcode (bits 0–5): 31
• Extended opcode: 982
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	icbi: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	icbi: read	Source GPR.

Register Effects

icbi

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

icbi

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="icbi"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:1183
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:32
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:850

Special Cases & Edge Conditions

• Self-modifying code primitive. Removes the line containing EA from the instruction cache so a subsequent fetch reads from memory. Required after writing new instructions because the I-cache is not coherent with the D-cache or with main memory.
• Standard recipe. The full sequence is: stw (write new code) → dcbst (push dirty data through D-cache to memory) → sync (wait for memory) → icbi (drop stale I-cache line) → isync (drain prefetch / refetch). Skipping any of these can leave the CPU executing stale instructions.
• Cache line size. Xenon's I-cache line is 128 bytes; the low seven bits of EA are ignored.
• RA0 semantics. When RA = 0, base is the literal zero. icbi 0, RB invalidates the line containing address RB.
• Unprivileged. icbi is problem-state, unlike its data-side cousin dcbi.
• No exception on bad address. Treated as a hint at the hardware level — invalidating an absent line is harmless.
• Per-thread effect. On the multithreaded Xenon core, icbi propagates across hardware threads sharing the same L1 I-cache; cross-core invalidation requires bus broadcast handled implicitly by the cache coherence protocol.
• Xenia models as no-op. No I-cache is simulated; rebuilds of generated code (when applicable) are triggered by the JIT cache-watcher, not by icbi itself.

Related Instructions

• dcbst — D-cache write-back (paired step before icbi).
• dcbf, dcbi — D-cache push / invalidate.
• isync — instruction-stream barrier (paired step after icbi).
• sync — full memory barrier between dcbst and icbi.

IBM Reference

• AIX 7.3 — icbi (Instruction Cache Block Invalidate)
• PowerISA v2.07B Book II § "Instruction Storage" for the canonical self-modifying-code sequence.