Sylpheed/tools/ppc-manual/alu/addi.md

addi — Add Immediate

Category: Integer ALU · Form: D · Opcode: 0x38000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
addi	addi	—	Add Immediate

Syntax

addi [RD], [RA0], [SIMM]

Encoding

addi — form D

• Opcode word: 0x38000000
• Primary opcode (bits 0–5): 14
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

Operands

Field	Role	Description
RA0	addi: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
SIMM	addi: read	16-bit signed immediate. Sign-extended to 64 bits before use.
RD	addi: write	Destination GPR.

Register Effects

addi

• Reads (always): RA0, SIMM
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

if RA = 0 then RT <- EXTS(SIMM)
else             RT <- (RA) + EXTS(SIMM)

C Translation Example

/* addi RT, RA, SIMM   — RA=0 means literal 0                      */
uint64_t base = (insn.RA == 0) ? 0 : r[insn.RA];
r[insn.RT] = base + (uint64_t)(int64_t)(int16_t)insn.SIMM;

Implementation References

addi

• Canary XML: tools/ppc-instructions.xml — search for mnem="addi"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:103
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:10
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:453

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_addi(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   RT <- EXTS(SI)
  // else
  //   RT <- (RA) + EXTS(SI)
  Value* si = f.LoadConstantInt64(XEEXTS16(i.D.DS));
  Value* v = si;
  if (i.D.RA) {
    v = f.Add(f.LoadGPR(i.D.RA), si);
  }
  f.StoreGPR(i.D.RT, v);
  return 0;
}

Special Cases & Edge Conditions

• RA0 semantics. When the encoded RA field is 0 the operand is the literal constant 0, not the value of r0. This lets addi rT, 0, SIMM load a constant (the li rT, SIMM simplified mnemonic). To use r0's value you must use a register-register add (add RT, r0, RB through a temp) or an instruction without RA0 semantics.
• No flags written. Unlike add, addi cannot be Rc or OE — no CR or XER update. Use addic if you need XER[CA], or addicx (addic.) if you need both XER[CA] and a CR0 update.
• Immediate is 16-bit signed (SIMM, range −32768 … +32767), sign-extended to 64 bits before the add. No carry/overflow is produced regardless of the result.
• Simplified mnemonics. Assemblers recognise several aliases that all assemble to addi:
  • li RT, SIMM ≡ addi RT, 0, SIMM (load immediate; relies on RA0).
  • la RT, D(RA) ≡ addi RT, RA, D (load address; purely syntactic).
  • subi RT, RA, SIMM ≡ addi RT, RA, −SIMM.
• PC-relative idiom. addi RT, RA, D is the low-half completion of a two-instruction address load preceded by addis RT, 0, HI. The assembler emits @ha/@l relocations so the low half can be negative without corrupting the high half (add-compensation).

Related Instructions

• addis — same encoding family but the immediate is shifted left by 16 bits. Together they build any 32-bit constant or PC-relative address.
• addic, addicx — D-form adds that do set XER[CA] (and CR0 for the record form).
• addx — the register-register form.
• subfic — reverse-subtract immediate (imm − RA) with carry.
• ori, oris — the alternative D-form constant-building instructions (but these don't add, they OR).

IBM Reference

• AIX 7.3 — addi (Add Immediate)
• AIX 7.3 — li (Load Immediate, simplified mnemonic)