Sylpheed/tools/ppc-manual/alu/cmpi.md

cmpi — Compare Immediate

Category: Integer ALU · Form: D · Opcode: 0x2c000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
cmpi	cmpi	—	Compare Immediate

Syntax

cmpi [CRFD], [L], [RA], [SIMM]

Encoding

cmpi — form D

• Opcode word: 0x2c000000
• Primary opcode (bits 0–5): 11
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

Operands

Field	Role	Description
L	cmpi: read	Operand-length bit for compare instructions (0 ⇒ 32-bit, 1 ⇒ 64-bit).
RA	cmpi: read	Source GPR (r0–r31).
SIMM	cmpi: read	16-bit signed immediate. Sign-extended to 64 bits before use.
RD	cmpi: write	Destination GPR.
CRFD	cmpi: write	CR destination field (crf, 0–7).

Register Effects

cmpi

• Reads (always): L, RA, SIMM
• Reads (conditional): none
• Writes (always): RD, CRFD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

if L = 0 then a,b <- EXTS((RA)[32:63]), EXTS(SIMM)
else             a,b <- (RA), EXTS(SIMM)
CR[BF] <- signed_compare(a, b) || XER[SO]

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

cmpi

• Canary XML: tools/ppc-instructions.xml — search for mnem="cmpi"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:552
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:28
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:450

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_cmpi(PPCHIRBuilder& f, const InstrData& i) {
  // if L = 0 then
  //   a <- EXTS((RA)[32:63])
  // else
  //   a <- (RA)
  // if a < EXTS(SI) then
  //   c <- 0b100
  // else if a > EXTS(SI) then
  //   c <- 0b010
  // else
  //   c <- 0b001
  // CR[4×BF+32:4×BF+35] <- c || XER[SO]
  uint32_t BF = i.D.RT >> 2;
  uint32_t L = i.D.RT & 1;
  Value* lhs;
  Value* rhs;
  if (L) {
    lhs = f.LoadGPR(i.D.RA);
    rhs = f.LoadConstantInt64(XEEXTS16(i.D.DS));
  } else {
    lhs = f.Truncate(f.LoadGPR(i.D.RA), INT32_TYPE);
    rhs = f.LoadConstantInt32(int32_t(XEEXTS16(i.D.DS)));
  }
  f.UpdateCR(BF, lhs, rhs);
  return 0;
}

Special Cases & Edge Conditions

• Immediate is sign-extended. SIMM is treated as a signed 16-bit value in the range [-32768, 32767] and sign-extended to the operand width. Use cmpli for unsigned comparisons against a 16-bit value.
• L bit selects width. L = 0 (the usual cmpwi) compares the low 32 bits of RA (sign-extended) against EXTS(SIMM); L = 1 (cmpdi) does a full 64-bit signed compare. Most Xbox 360 code uses cmpwi because pointers and counters are 32-bit ABI.
• Simplified mnemonics dominate disassembly. cmpwi crN, RA, SIMM ≡ cmpi crN, 0, RA, SIMM and cmpdi crN, RA, SIMM ≡ cmpi crN, 1, RA, SIMM. The default CR field is cr0 if omitted.
• BF is a CR field (0–7), not a bit. Same convention as cmp. Distinct standalone compares should target cr1..cr7 to avoid clobbering the implicit cr0 chain set up by Rc=1 arithmetic.
• SO is copied from XER[SO]. This makes overflow observable downstream of an addo. / mulo. etc. via bso/bns.
• Canary is one direct compare. As in cmp: the operand and EXTS(SI) are compared at 64 or 32 bits by L, via f.UpdateCR(BF, lhs, rhs), which does not write the field's SO bit (spec copies XER[SO]).
• No register written other than the 4-bit CR field — there is no Rc or OE bit.

Related Instructions

• cmp — register-register signed compare.
• cmpli — unsigned compare against immediate (zero-extended).
• cmpl — unsigned register compare.
• cmpwi, cmpdi (simplified mnemonics) — select L=0 / L=1.
• mcrxr — clear sticky overflow before a fresh compare sequence.

IBM Reference

• AIX 7.3 — cmpi (Compare Immediate)
• AIX 7.3 — cmpwi / cmpdi (simplified mnemonics)