Sylpheed/tools/ppc-manual/vmx/vadduhs.md

vadduhs — Vector Add Unsigned Half Word Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000240

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vadduhs	vadduhs	—	Vector Add Unsigned Half Word Saturate

Syntax

vadduhs [VD], [VA], [VB]

Encoding

vadduhs — form VX

• Opcode word: 0x10000240
• Primary opcode (bits 0–5): 4
• Extended opcode: 576
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vadduhs: read	Source A vector register.
VB	vadduhs: read	Source B vector register.
VD	vadduhs: write	Destination vector register.
VSCR	vadduhs: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vadduhs

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vadduhs: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vadduhs

• Canary XML: tools/ppc-instructions.xml — search for mnem="vadduhs"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:394
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:304
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:597

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vadduhs(PPCHIRBuilder& f, const InstrData& i) {
  Value* v = f.VectorAdd(f.LoadVR(i.VX.VA), f.LoadVR(i.VX.VB), INT16_TYPE,
                         ARITHMETIC_UNSIGNED | ARITHMETIC_SATURATE);
  f.StoreSAT(f.DidSaturate(v));
  f.StoreVR(i.VX.VD, v);
  return 0;
}

Special Cases & Edge Conditions

• Eight unsigned-half lanes, saturating. Each VD[i] = min(VA[i] + VB[i], 0xFFFF) for i = 0..7. Lane 0 (VD[0..1] after stvx) is the most-significant half.
• VSCR[SAT] is sticky-set if any lane clamps. Cleared only by mtvscr. ⚠️ Canary never records SAT: its StoreSAT(DidSaturate(v)) writes a private vscr_sat byte, the x64 DID_SATURATE is a stub that always yields 0, and mfvscr reads vscr_vec, which only mtvscr changes.
• One-sided clamp. Unsigned add cannot underflow, so only the upper bound 0xFFFF ever clips.
• The modulo counterpart is vadduhm. Use vadduhs when "too large to fit" must be flagged or clipped — typical for accumulating Q16 unsigned counters.
• No XER side effects.
• Maps directly to _mm_adds_epu16 on SSE2 hosts — semantically identical for the lanes. Canary emits a saturating unsigned VectorAdd but never records VSCR[SAT] (x64 DID_SATURATE is a stub).
• No VMX128 sibling.

Related Instructions

• vadduhm — same width, modulo (non-saturating) add.
• vaddshs — same width, signed saturating add (range -32768..+32767).
• vaddubs, vadduws — unsigned saturating add at byte / word width.
• vsubuhs — the matching unsigned saturating subtract.
• mtvscr / mfvscr — read or clear the sticky VSCR[SAT] bit.

IBM Reference

• AIX 7.3 — vadduhs (Vector Add Unsigned Half Word Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Saturating Integer Arithmetic