Sylpheed/tools/ppc-manual/vmx/vpkuwum.md

vpkuwum — Vector Pack Unsigned Word Unsigned Modulo

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000004e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vpkuwum	vpkuwum	—	Vector Pack Unsigned Word Unsigned Modulo
vpkuwum128	vpkuwum128	—	Vector128 Pack Unsigned Word Unsigned Modulo

Syntax

vpkuwum [VD], [VA], [VB]
vpkuwum128 [VD], [VA], [VB]

Encoding

vpkuwum — form VX

• Opcode word: 0x1000004e
• Primary opcode (bits 0–5): 4
• Extended opcode: 78
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vpkuwum128 — form VX128

• Opcode word: 0x14000380
• Primary opcode (bits 0–5): 5
• Extended opcode: 896
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vpkuwum: read; vpkuwum128: read	Source A vector register.
VB	vpkuwum: read; vpkuwum128: read	Source B vector register.
VD	vpkuwum: write; vpkuwum128: write	Destination vector register.

Register Effects

vpkuwum

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vpkuwum128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vpkuwum

• Canary XML: tools/ppc-instructions.xml — search for mnem="vpkuwum"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1959
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:417
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:562

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vpkuwum(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vpkuwum_(f, i.VX.VD, i.VX.VA, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1946) ──
int InstrEmit_vpkuwum_(PPCHIRBuilder& f, uint32_t vd, uint32_t va,
                       uint32_t vb) {
  // Vector Pack Unsigned Word Unsigned Modulo
  // Concat low shorts from VA + VB:
  // for each i in VA + VB:
  //   i = uint16_t(uint32_t(i))
  // dest = VA | VB (lower 16bit values)
  Value* v = f.Pack(f.LoadVR(va), f.LoadVR(vb),
                    PACK_TYPE_16_IN_32 | PACK_TYPE_IN_UNSIGNED |
                        PACK_TYPE_OUT_UNSIGNED | PACK_TYPE_OUT_UNSATURATE);
  f.StoreVR(vd, v);
  return 0;
}

vpkuwum128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vpkuwum128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1962
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:418
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:745

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vpkuwum128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vpkuwum_(f, VX128_VD128, VX128_VA128, VX128_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1946) ──
int InstrEmit_vpkuwum_(PPCHIRBuilder& f, uint32_t vd, uint32_t va,
                       uint32_t vb) {
  // Vector Pack Unsigned Word Unsigned Modulo
  // Concat low shorts from VA + VB:
  // for each i in VA + VB:
  //   i = uint16_t(uint32_t(i))
  // dest = VA | VB (lower 16bit values)
  Value* v = f.Pack(f.LoadVR(va), f.LoadVR(vb),
                    PACK_TYPE_16_IN_32 | PACK_TYPE_IN_UNSIGNED |
                        PACK_TYPE_OUT_UNSIGNED | PACK_TYPE_OUT_UNSATURATE);
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

• Unsigned word → half-word modulo pack. Each of the 8 input word lanes is truncated to its low 16 bits.
• Lane-count doubling. 4+4 word lanes → 8 half-word lanes; VA's 4 words into VD.h[0..3], VB's into VD.h[4..7].
• VSCR[SAT] never touched (modulo variant). Use vpkuwus for saturation.
• Cheap low-half extract. Typical after a 32-bit lane accumulator is "narrowed" back down to 16-bit for storage.
• No Rc, no XER.
• VMX128 sibling vpkuwum128.

Related Instructions

• vpkuwus — saturating counterpart.
• vpkuhum — half-word → byte modulo.
• vpkswss, vpkswus — signed word inputs.
• vupkhsh, vupklsh — signed-half-word → word unpacks.
• vperm — alternative for irregular patterns.

IBM Reference

• AIX 7.3 — vpkuwum (Vector Pack Unsigned Word Unsigned Modulo)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting