Sylpheed/tools/ppc-manual/vmx/vsldoi.md

vsldoi — Vector Shift Left Double by Octet Immediate

Category: VMX (Altivec) · Form: VA · Opcode: 0x1000002c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vsldoi	vsldoi	—	Vector Shift Left Double by Octet Immediate
vsldoi128	vsldoi128	—	Vector128 Shift Left Double by Octet Immediate

Syntax

vsldoi [VD], [VA], [VB], [SHB]
vsldoi128 [VD], [VA], [VB], [SHB]

Encoding

vsldoi — form VA

• Opcode word: 0x1000002c
• Primary opcode (bits 0–5): 4
• Extended opcode: 44
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT	destination vector register
11–15	VRA	source A
16–20	VRB	source B
21–25	VRC	source C / shift
26–31	XO	extended opcode (6 bits)

vsldoi128 — form VX128_5

• Opcode word: 0x10000010
• Primary opcode (bits 0–5): 4
• Extended opcode: 16
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22–25	SH	4-bit shift amount
26	VA128h	source A middle bit
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vsldoi: read; vsldoi128: read	Source A vector register.
VB	vsldoi: read; vsldoi128: read	Source B vector register.
SHB	vsldoi: read; vsldoi128: read	Shift amount (byte granularity, vsldoi).
VD	vsldoi: write; vsldoi128: write	Destination vector register.

Register Effects

vsldoi

• Reads (always): VA, VB, SHB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vsldoi128

• Reads (always): VA, VB, SHB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vsldoi

• Canary XML: tools/ppc-instructions.xml — search for mnem="vsldoi"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1463
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:442
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:702

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vsldoi(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vsldoi_(f, i.VXA.VD, i.VXA.VA, i.VXA.VB, i.VXA.VC & 0xF);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1434) ──
int InstrEmit_vsldoi_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb,
                      uint32_t sh) {
  // (VD) <- ((VA) || (VB)) << (SH << 3)
  if (!sh) {
    f.StoreVR(vd, f.LoadVR(va));
    return 0;
  } else if (sh == 16) {
    f.StoreVR(vd, f.LoadVR(vb));
    return 0;
  }
  Value* v;
  if (!(sh & 3)) {
    // Word-aligned shifts can use the cheaper 32-bit permute.
    uint32_t control = 0;
    uint32_t source_word = sh >> 2;
    for (uint32_t output_word = 0; output_word < 4;
         ++output_word, ++source_word) {
      control |= ((source_word & 3) | ((source_word & 4) ? 4 : 0))
                 << (output_word * 8);
    }
    v = f.Permute(f.LoadConstantUint32(control), f.LoadVR(va), f.LoadVR(vb),
                  INT32_TYPE);
  } else {
    Value* control = f.LoadConstantVec128(__vsldoi_table[sh]);
    v = f.Permute(control, f.LoadVR(va), f.LoadVR(vb), INT8_TYPE);
  }
  f.StoreVR(vd, v);
  return 0;
}

vsldoi128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vsldoi128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1466
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:443
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:710

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vsldoi128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vsldoi_(f, VX128_5_VD128, VX128_5_VA128, VX128_5_VB128,
                           VX128_5_SH);
}

Special Cases & Edge Conditions

• Static byte-level shift of VA ‖ VB. The 4-bit SHB immediate names a byte offset into the 32-byte concatenation VA ‖ VB. The destination VD is the 16-byte window starting at that offset. Equivalently: VD = (VA << (8 * SHB)) | (VB >> (8 * (16 − SHB))), treating the 32-byte concatenation as a single big-endian value.
• SHB = 0 is a register move from VA to VD. SHB = 16 is ill-formed; the field is 4 bits (0..15) so the range is SHB ∈ 0..=15.
• Compile-time shift only. Unlike vperm / vslo / vsro, the shift is an immediate. When the shift is known at compile time, vsldoi is strictly cheaper than an lvsl + vperm pair.
• Unaligned-load idiom. vsldoi is the static-offset counterpart to the dynamic lvsl + vperm pattern. When the misalignment is known, emit vsldoi vD, vAL, vAH, SHB after two aligned lvx loads.
• Big-endian byte indexing. Lane 0 is the MSB.
• No flags, no VSCR.
• VMX128 sibling vsldoi128 with the wider register file; same 4-bit SHB immediate.

Related Instructions

• vslo, vsro — byte-level (octet) shifts using a per-register count, dynamic.
• vsl, vsr — bit-level whole-register shifts.
• vperm — general-purpose programmable byte permute.
• lvsl, lvsr — dynamic permute-control generators.
• vmrghb, vmrglb — byte-granularity merges.

IBM Reference

• AIX 7.3 — vsldoi (Vector Shift Left Double by Octet Immediate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting