Sylpheed/tools/ppc-manual/alu/cntlzdx.md

cntlzdx — Count Leading Zeros Doubleword

Category: Integer ALU · Form: X · Opcode: 0x7c000074

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
cntlzd	cntlzdx	—	Count Leading Zeros Doubleword
cntlzd.	cntlzdx	Rc=1	Count Leading Zeros Doubleword

Syntax

cntlzd [RA], [RS]

Encoding

cntlzdx — form X

• Opcode word: 0x7c000074
• Primary opcode (bits 0–5): 31
• Extended opcode: 58
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	cntlzdx: read	Source GPR (alias for RD in some stores).
RA	cntlzdx: write	Source GPR (r0–r31).
CR	cntlzdx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

cntlzdx

• Reads (always): RS
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• cntlzdx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

n <- number_of_leading_zero_bits((RS))           ; n in 0..64
RA <- zero_extend(n)

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

cntlzdx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="cntlzdx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:674
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:15
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:767
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:615-619

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::cntlzdx => {
            ctx.gpr[instr.ra()] = ctx.gpr[instr.rs()].leading_zeros() as u64;
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Result range is 0..=64. When RS == 0, every bit is a leading zero and RA = 64. When the high bit (RS[0]) is set, RA = 0. Any intermediate value yields the count of high-order zeros before the first 1-bit.
• Counts across the full 64 bits. Use cntlzwx when you only want to count the low 32 bits.
• Useful as floor(log2(x)) = 63 − cntlzd(x) for nonzero x. Frequently used in fast normalization, priority encoders, and bit-vector operations.
• RB field unused. This is X-form but only RS is read; RB is a placeholder slot.
• Rc=1 quirk. update_cr_signed(0, RA as i64) is correct in xenia-rs because the result fits in 7 bits and is non-negative. The CR0 result will always be EQ (when RS != 0 and RA != 0? — actually EQ only when RS[0] == 1, i.e. RA == 0) or GT (when RS != 0 so RA > 0); never LT. EQ corresponds to "high bit set in RS", a useful one-instruction sign test for negative-as-signed values.
• No XER side effects. Counts neither overflow nor carry.

Related Instructions

• cntlzwx — 32-bit version (counts only RS[32:63]).
• sldx, srdx — pair with cntlzd for normalisation.
• rldiclx — for extracting individual bit positions once the leading-zero count is known.
• cmpi / cmp — alternative for testing the high bit.

IBM Reference

• AIX 7.3 — cntlzd (Count Leading Zeros Doubleword)