Sylpheed/tools/ppc-manual/alu/rldimix.md

rldimix — Rotate Left Doubleword Immediate then Mask Insert

Category: Integer ALU · Form: MD · Opcode: 0x7800000c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
rldimi	rldimix	—	Rotate Left Doubleword Immediate then Mask Insert
rldimi.	rldimix	Rc=1	Rotate Left Doubleword Immediate then Mask Insert

Syntax

rldimi[Rc] [RA], [RS], [SH], [MB]

Encoding

rldimix — form MD

• Opcode word: 0x7800000c
• Primary opcode (bits 0–5): 30
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (30)
6–10	RS	source GPR
11–15	RA	destination GPR
16–20	sh	shift amount low 5 bits
21–26	mb/me	6-bit mask field (swapped halves)
27–29	XO	extended opcode
30	sh5	shift amount high bit
31	Rc	record-form flag

Operands

Field	Role	Description
RS	rldimix: read	Source GPR (alias for RD in some stores).
SH	rldimix: read	Shift amount.
MB	rldimix: read	Mask begin bit.
RA	rldimix: write	Source GPR (r0–r31).
CR	rldimix: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

rldimix

• Reads (always): RS, SH, MB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• rldimix: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

rldimix

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="rldimix"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:985
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:61
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:731
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:792-801

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::rldimix => {
            let rs = ctx.gpr[instr.rs()];
            let sh = instr.sh64();
            let mb = instr.mb_md();
            let rotated = rs.rotate_left(sh);
            let mask = rld_mask_left(mb) & rld_mask_right(63 - sh);
            ctx.gpr[instr.ra()] = (rotated & mask) | (ctx.gpr[instr.ra()] & !mask);
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• RA ← (ROTL64(RS, SH) & MASK) | (RA & ~MASK). Reads the prior RA so it can preserve the bits outside the mask — this is the only rld* instruction with RA as both source and destination.
• Mask is MASK_LEFT(MB) AND MASK_RIGHT(63 - SH) (interpreter.rs:578) — same span as rldicx, but the un-masked region is preserved in the destination instead of being zeroed.
• Use to insert a bit-field. Common idiom: rldimi RA, RS, b, mask_start writes RS's low (64 - mask_start) bits into RA starting at bit b.
• SH and MB decoding is identical to the rest of the family (6-bit sh via instr.sh64(), 6-bit mb via the swap layout).
• Rc=1 CR0 is correctly 64-bit. Uses as i64 directly.
• No XER effect.
• Compile-time pattern. When you see rldimi r3, r4, n, m, the compiler is splicing a value into r3; recover the meaning by computing the mask MASK(m, 63 - n).

Related Instructions

• rldicx, rldiclx, rldicrx — same form family, but they zero outside the mask instead of preserving.
• rlwimix — 32-bit insert cousin.
• rldclx, rldcrx — register-shift forms (no insert variant).

IBM Reference

• AIX 7.3 — rldimi (Rotate Left Doubleword Immediate then Mask Insert)