Sylpheed/tools/ppc-manual/alu/cntlzwx.md

cntlzwx — Count Leading Zeros Word

Category: Integer ALU · Form: X · Opcode: 0x7c000034

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
cntlzw	cntlzwx	—	Count Leading Zeros Word
cntlzw.	cntlzwx	Rc=1	Count Leading Zeros Word

Syntax

cntlzw[Rc] [RA], [RS]

Encoding

cntlzwx — form X

• Opcode word: 0x7c000034
• Primary opcode (bits 0–5): 31
• Extended opcode: 26
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	cntlzwx: read	Source GPR (alias for RD in some stores).
RA	cntlzwx: write	Source GPR (r0–r31).
CR	cntlzwx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

cntlzwx

• Reads (always): RS
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• cntlzwx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

n <- number_of_leading_zero_bits((RS)[32:63])    ; n in 0..32
RA <- zero_extend(n)

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

cntlzwx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="cntlzwx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:689
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:15
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:758
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:608-614

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::cntlzwx => {
            // Result is 0..=32, fits in u32 with bit 31 always zero, so the
            // CR0 view is benign — use the catch-all 32-bit form for consistency.
            ctx.gpr[instr.ra()] = (ctx.gpr[instr.rs()] as u32).leading_zeros() as u64;
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as u32 as i32 as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Operates only on the low 32 bits. RS[0:31] is ignored; the count is taken on RS[32:63]. Result range is 0..=32.
• RA = 32 when the low 32 bits are zero, regardless of the high 32 bits. A common pitfall: cntlzw after computing a 64-bit value can give a counter-intuitive result when the leading 1-bit lives in the high half.
• RA = 0 when bit 32 (the sign bit of the low word) is set. This makes cntlzw RA, RS; cmpwi RA, 0 a one-instruction-pair "is the low half negative" test, though srawi RA, RS, 31 is more idiomatic.
• High 32 bits of the result are zero. RA[0:31] = 0, RA[32:63] = count.
• Rc=1 CR0 update is small-positive-only. Result fits in 6 bits; xenia's as i32 as i64 truncation in interpreter.rs:404 is harmless. CR0 will be EQ only when RS[32] (sign bit of low word) is 1, otherwise GT.
• Useful for floor(log2) of a 32-bit value. 31 - cntlzw(x) for nonzero x.

Related Instructions

• cntlzdx — 64-bit version (counts the full register).
• slwx, srwx, srawx — 32-bit shifts often paired with cntlzw for normalisation.
• rlwinmx — to mask off bits before counting.
• cmpi, cmpl — alternative ways to detect zero or sign.

IBM Reference

• AIX 7.3 — cntlzw (Count Leading Zeros Word)