Sylpheed/tools/ppc-manual/alu/divwx.md

divwx — Divide Word

Category: Integer ALU · Form: XO · Opcode: 0x7c0003d6

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
divw	divwx	—	Divide Word
divwo	divwx	OE=1	Divide Word
divw.	divwx	Rc=1	Divide Word
divwo.	divwx	OE=1, Rc=1	Divide Word

Syntax

divw[OE][Rc] [RD], [RA], [RB]

Encoding

divwx — form XO

• Opcode word: 0x7c0003d6
• Primary opcode (bits 0–5): 31
• Extended opcode: 491
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	divwx: read	Source GPR (r0–r31).
RB	divwx: read	Source GPR.
RD	divwx: write	Destination GPR.
OE	divwx: write (conditional)	Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow.
CR	divwx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

divwx

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): OE, CR

Status-Register Effects

• divwx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, when OE=1.

Operation (pseudocode)

RT <- ((RA)[32:63] /s (RB)[32:63]) sign-extended to 64 ; undefined if RB=0 or overflow

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

divwx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="divwx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:242
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:21
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:879
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:394-412

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::divwx => {
            // PPCBUG-010+011 coupled: 32-bit ABI. Quotient zero-extended to u64
            // (canary explicitly uses ZeroExtend(v, INT64_TYPE)). CR0 view via i32.
            let ra = ctx.gpr[instr.ra()] as i32;
            let rb = ctx.gpr[instr.rb()] as i32;
            let ov = overflow::divw_ov_signed(ra, rb);
            if ov {
                ctx.gpr[instr.rd()] = 0;
            } else {
                ctx.gpr[instr.rd()] = (ra / rb) as u32 as u64;
            }
            if instr.oe() {
                overflow::apply(ctx, ov);
            }
            if instr.rc_bit() {
                ctx.update_cr_signed(0, ctx.gpr[instr.rd()] as u32 as i32 as i64);
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• 32-bit operands, sign-extended result. Both RA and RB are read as their low 32 bits, signed; the quotient is computed as i32, then sign-extended to 64 bits before being stored in RT. The high 32 bits of RA/RB are ignored.
• Two undefined cases: RB == 0 and RA == INT32_MIN && RB == -1 (quotient 2^31 is unrepresentable). Xenia-rs returns 0 for both (interpreter.rs:238); PowerISA leaves RT boundedly undefined.
• No trap on Xenon. Like divdx, the processor silently produces an undefined value instead of raising an exception.
• OE=1 should set XER[OV] in both undefined cases; xenia-rs does not implement this.
• Rc=1 CR0 update truncates to 32 bits in xenia-rs. interpreter.rs:243 uses as i32 as i64. This is correct for divw because the result is already a sign-extended 32-bit value — high bits agree with the low-32 sign extension. So spec and xenia agree for this instruction.
• Truncating quotient. Rounds toward zero, matching C / for int32_t.
• Slow. Same ~30-cycle non-pipelined cost as 64-bit divide; faster than divd because the underlying datapath is narrower but still much slower than multiply-then-shift reciprocal sequences.

Related Instructions

• divwux — unsigned 32-bit divide.
• divdx, divdux — 64-bit variants.
• mullwx — pair with subtract to obtain the remainder.
• extsw — manual sign-extend if you only have a 64-bit value but want 32-bit divide semantics.

IBM Reference

• AIX 7.3 — divw (Divide Word)