Sylpheed/tools/ppc-manual/control/mffsx.md

mffsx — Move from FPSCR

Category: Control / CR / SPR · Form: X · Opcode: 0xfc00048e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mffs	mffsx	—	Move from FPSCR
mffs.	mffsx	Rc=1	Move from FPSCR

Syntax

mffs[Rc] [RD]

Encoding

mffsx — form X

• Opcode word: 0xfc00048e
• Primary opcode (bits 0–5): 63
• Extended opcode: 583
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FPSCR	mffsx: read	Floating-Point Status and Control Register.
FD	mffsx: write	Destination floating-point register.
CR	mffsx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

mffsx

• Reads (always): FPSCR
• Reads (conditional): none
• Writes (always): FD
• Writes (conditional): CR

Status-Register Effects

• mffsx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mffsx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="mffsx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:397
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:53
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:910
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3035-3040

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::mffsx => {
            // Move from FPSCR: frD = FPSCR as double (low 32 bits)
            ctx.fpr[instr.rd()] = f64::from_bits(ctx.fpscr as u64);
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Operation. Reads the 32-bit FPSCR and places it in the low 32 bits of FRT. The high 32 bits of the destination FPR are architecturally undefined; xenia leaves them as the bit-pattern of the FPSCR cast to u64 (i.e. the high bits are zero, since FPSCR is 32-bit). PowerISA explicitly permits implementations to leave anything there.
• Destination is an FPR, not a GPR. Use stfd to spill the FPR to memory and reload via a GPR if the value is needed in the integer file.
• mffs. (Rc=1) updates CR1. The Rc bit copies the high four FPSCR bits (FX, FEX, VX, OX) into CR1's LT/GT/EQ/SO. xenia-rs implements this via update_cr1_from_fpscr.
• No FPSCR side effect. Pure read; FPSCR is not modified (unlike mcrfs, which clears sticky exception bits).
• xenia simplification. xenia-rs models FPSCR as a u32 field but does not actively maintain most of the IEEE-754 sticky bits — the FPU paths typically leave FPSCR untouched. So mffs will return whatever was last explicitly set (often 0 / boot defaults). Real titles use it mostly to save/restore the rounding-mode field around library calls, which xenia happens to handle correctly.
• Not synchronising. Reorderable with non-FPU instructions.

Related Instructions

• mtfsfx — write fields of FPSCR from an FPR (the inverse).
• mtfsb0x, mtfsb1x — set/clear individual FPSCR bits.
• mtfsfix — load a 4-bit immediate into one FPSCR field.
• mcrfs — copy an FPSCR field into a CR field (and clear sticky bits).
• mfspr — for non-FPSCR special registers.

mffs is the simplified mnemonic for the base form (Rc=0); mffs. is the recording variant.

IBM Reference

• AIX 7.3 — mffs (Move from FPSCR)
• PowerISA v2.07B, Book I §4.6 — FPSCR layout and the high-half-undefined rule.