Sylpheed/tools/ppc-manual/memory/lvxl.md

lvxl — Load Vector Indexed LRU

Category: Memory · Form: X · Opcode: 0x7c0002ce

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lvxl	lvxl	—	Load Vector Indexed LRU
lvxl128	lvxl128	—	Load Vector Indexed LRU 128

Syntax

lvslx [VD], [RA0], [RB]
lvxl128 [VD], [RA0], [RB]

Encoding

lvxl — form X

• Opcode word: 0x7c0002ce
• Primary opcode (bits 0–5): 31
• Extended opcode: 359
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

lvxl128 — form VX128_1

• Opcode word: 0x100002c3
• Primary opcode (bits 0–5): 4
• Extended opcode: 707
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	RA	address register
16–20	RB	offset register
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	—	reserved

Operands

Field	Role	Description
RA0	lvxl: read; lvxl128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	lvxl: read; lvxl128: read	Source GPR.
VD	lvxl: write; lvxl128: write	Destination vector register.

Register Effects

lvxl

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

lvxl128

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lvxl

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lvxl"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:145
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:47
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:802
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1960-1969

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lvxl | PpcOpcode::lvxl128 => {
            // Same as lvx but with cache hint (ignored)
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = (ea.wrapping_add(ctx.gpr[instr.rb()]) & !0xF) as u32;
            let mut bytes = [0u8; 16];
            for i in 0..16 { bytes[i] = mem.read_u8(ea + i as u32); }
            let vd = if matches!(instr.opcode, PpcOpcode::lvxl128) { instr.vd128() } else { instr.rd() };
            ctx.vr[vd] = xenia_types::Vec128::from_bytes(bytes);
            ctx.pc += 4;
        }

lvxl128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lvxl128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:148
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:47
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:418
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1960-1969

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lvxl | PpcOpcode::lvxl128 => {
            // Same as lvx but with cache hint (ignored)
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = (ea.wrapping_add(ctx.gpr[instr.rb()]) & !0xF) as u32;
            let mut bytes = [0u8; 16];
            for i in 0..16 { bytes[i] = mem.read_u8(ea + i as u32); }
            let vd = if matches!(instr.opcode, PpcOpcode::lvxl128) { instr.vd128() } else { instr.rd() };
            ctx.vr[vd] = xenia_types::Vec128::from_bytes(bytes);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Same data effect as lvx, but with cache hint. Loads 16 bytes from EA & ~0xF into VD. The l suffix signals to the cache hardware that the line is least-recently-used — a hint that the line will not be reused soon, allowing the cache to evict it preferentially under pressure. Useful in streaming reads (e.g. once-through vertex transforms, decode passes).
• Hint ignored under emulation. Xenia's snapshot comment is explicit: "Same as lvx but with cache hint (ignored)". The functional behaviour is identical to lvx — only real hardware acts on the hint.
• Alignment is forced, not checked. Like lvx, the low four bits of EA are masked. Unaligned EA silently rounds down to the 16-byte boundary.
• Big-endian lane layout. Byte at the aligned base goes into lane 0; byte at base+15 into lane 15.
• RA0 semantics. RA = 0 selects literal zero.
• No update form. lvxl has no u-suffix variant.
• VMX128 sibling (lvxl128). Identical semantics; the only difference is the operand encoding using the split-field 7-bit register index addressing v0..v127. Xenia's snapshot dispatches on the opcode to decide which decode helper to use.
• Note: assembler typo. The Syntax block above shows lvslx for the non-128 variant — that is a transcription artefact of the source XML. The real mnemonic is lvxl.

Related Instructions

• lvx, lvx128 — same load without the LRU hint.
• stvxl, stvxl128 — symmetric "store last" variants.
• stvx — non-hint store.
• dcbt, dcbtst — explicit prefetch hints (the hint family).

IBM Reference

• AIX 7.3 — lvxl (Load Vector Indexed LRU)
• PowerISA v2.07B Book I "Vector Facility" for canonical hint semantics.