Sylpheed/tools/ppc-manual/memory/stfs.md

stfs — Store Floating-Point Single

Category: Memory · Form: D · Opcode: 0xd0000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stfs	stfs	—	Store Floating-Point Single
stfsu	stfsu	—	Store Floating-Point Single with Update
stfsux	stfsux	—	Store Floating-Point Single with Update Indexed
stfsx	stfsx	—	Store Floating-Point Single Indexed

Syntax

stfs [FS], [d]([RA0])
stfsu [FS], [d]([RA])
stfsux [FS], [RA], [RB]
stfsx [FS], [RA], [RB]

Encoding

stfs — form D

• Opcode word: 0xd0000000
• Primary opcode (bits 0–5): 52
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

stfsu — form D

• Opcode word: 0xd4000000
• Primary opcode (bits 0–5): 53
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

stfsux — form X

• Opcode word: 0x7c00056e
• Primary opcode (bits 0–5): 31
• Extended opcode: 695
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

stfsx — form X

• Opcode word: 0x7c00052e
• Primary opcode (bits 0–5): 31
• Extended opcode: 663
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FS	stfs: read; stfsu: read; stfsux: read; stfsx: read	Source floating-point register.
RA0	stfs: read; stfsx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
d	stfs: read; stfsu: read	16-bit signed displacement (d) added to the base address register.
RA	stfsu: read; stfsu: write; stfsux: read; stfsux: write	Source GPR (r0–r31).
RB	stfsux: read; stfsx: read	Source GPR.

Register Effects

stfs

• Reads (always): FS, RA0, d
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

stfsu

• Reads (always): FS, RA, d
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): none

stfsux

• Reads (always): FS, RA, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): none

stfsx

• Reads (always): FS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

EA <- (RA|0) + EXTS(d)
MEM(EA, 4) <- SingleFromDouble(FRS)

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stfs

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stfs"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:1071
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:71
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:375
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1437-1445

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stfs => {
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = ea.wrapping_add(instr.d() as i64 as u64) as u32;
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() { t.invalidate_for_write(ea); }
            }
            mem.write_f32(ea, ctx.fpr[instr.rs()] as f32);
            ctx.pc += 4;
        }

stfsu

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stfsu"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:1084
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:71
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:376
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1446-1454

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stfsu => {
            let ea = ctx.gpr[instr.ra()].wrapping_add(instr.d() as i64 as u64) as u32;
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() { t.invalidate_for_write(ea); }
            }
            mem.write_f32(ea, ctx.fpr[instr.rs()] as f32);
            ctx.gpr[instr.ra()] = ea as u64;
            ctx.pc += 4;
        }

stfsux

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stfsux"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:1095
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:71
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:834
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1464-1472

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stfsux => {
            let ea = ctx.gpr[instr.ra()].wrapping_add(ctx.gpr[instr.rb()]) as u32;
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() { t.invalidate_for_write(ea); }
            }
            mem.write_f32(ea, ctx.fpr[instr.rs()] as f32);
            ctx.gpr[instr.ra()] = ea as u64;
            ctx.pc += 4;
        }

stfsx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stfsx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:1106
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:71
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:832
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1455-1463

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stfsx => {
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() { t.invalidate_for_write(ea); }
            }
            mem.write_f32(ea, ctx.fpr[instr.rs()] as f32);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Double → single rounding. FRS always holds an IEEE binary64; stfs rounds to binary32 using the current FPSCR[RN] rounding mode before writing 4 bytes. The xenia snapshot does ctx.fpr[instr.rs()] as f32, which Rust defines as round-to-nearest-even; this differs from PPC if RN is configured otherwise. Real hardware honours RN.
• FPSCR side effects. Unlike lfs / lfd / stfd, stfs can raise FPSCR[XX] (inexact), OX (overflow), UX (underflow), and VXSNAN (signalling NaN) per IEEE-754 narrowing rules. These take effect even though the write itself succeeds (architecturally — xenia's as f32 cast does not surface these flags).
• Out-of-range doubles. Values larger than binary32's max (~3.4e38) round to ±∞; values smaller than min normal flush to ±0 or denormal per FPSCR[NI]. NaNs are quieted (the signalling bit drops).
• RA0 (non-update forms). RA = 0 in stfs and stfsx selects literal zero. Update forms stfsu / stfsux invoke RA = 0 as an invalid form.
• Update-form post-write. stfsu / stfsux write EA back to RA after the store.
• Big-endian write. 4 bytes most-significant-byte first.
• Alignment. Xenon tolerates unaligned 4-byte FP stores; cache-inhibited storage may raise alignment exceptions on real hardware.
• MSR[FP] required. Disabled FP unit raises Floating-Point Unavailable.

Related Instructions

• lfs, lfsu, lfsx, lfsux — corresponding loads (single→double widening, can't raise exceptions).
• stfd — double-precision store (no rounding, no FPSCR effects).
• stfiwx — store-FP-as-integer-word.
• stw — integer word store (same width, GPR source).

IBM Reference

• AIX 7.3 — stfs (Store Floating-Point Single)
• AIX 7.3 — stfsu / stfsx / stfsux