Sylpheed/tools/ppc-manual/memory/stvebx.md

stvebx — Store Vector Element Byte Indexed

Category: Memory · Form: X · Opcode: 0x7c00010e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stvebx	stvebx	—	Store Vector Element Byte Indexed

Syntax

stvebx [VS], [RA0], [RB]

Encoding

stvebx — form X

• Opcode word: 0x7c00010e
• Primary opcode (bits 0–5): 31
• Extended opcode: 135
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
VS	stvebx: read	Source vector register (alias for VD on stores).
RA0	stvebx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	stvebx: read	Source GPR.

Register Effects

stvebx

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stvebx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stvebx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:152
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:77
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:778
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1914-1926

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stvebx => {
            // Store vS[EA & 0xF] (1 byte) to memory at EA.
            let base = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = base.wrapping_add(ctx.gpr[instr.rb()]) as u32;
            // PPCBUG-512: stvebx was missing invalidate_for_write.
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() { t.invalidate_for_write(ea); }
            }
            let slot = (ea & 0xF) as usize;
            let bytes = ctx.vr[instr.rs()].as_bytes();
            mem.write_u8(ea, bytes[slot]);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Single-byte element store. Architecturally stvebx writes exactly one byte from lane EA mod 16 of VS to address EA. Other lanes are unaffected, and other memory bytes are unaffected.
• Xenia simplification — full 16-byte write. The xenia snapshot is shared with stvehx / stvewx and writes the entire 16-byte aligned line (ea & ~0xF, then 16 bytes from the vector). This is stronger than the architectural single-byte store — it overwrites 15 adjacent bytes with whatever the source vector holds. Code that depends on architectural per-byte granularity (e.g. interleaved writes from multiple threads / DMA agents into the same line) may behave differently than on hardware.
• RA0 semantics. RA = 0 selects literal zero.
• No update form, no VMX128 sibling. No stvebux; no stvebx128 — single-byte stores were kept Altivec-only in the Xbox 360 extension.
• Big-endian within the line. Lane 0 of VS corresponds to the byte at the aligned base address.
• Common idiom. Pair with vsplt* to broadcast a value, then stvebx to write one byte. Less efficient than stb from a GPR; rare in compiled code.
• Hardware fault model. A protected or unmapped page raises a DSI exception just as for any store.

Related Instructions

• stvehx, stvewx — single half / single word element stores.
• stvx, stvxl — full 16-byte aligned vector stores.
• stvlx, stvrx — store-left / store-right unaligned vector ops.
• lvebx — symmetric single-byte load.

IBM Reference

• AIX 7.3 — stvebx (Store Vector Element Byte Indexed)
• PowerISA v2.07B Book I "Vector Facility" § "Vector Load and Store" for canonical per-byte semantics.