Sylpheed/tools/ppc-manual/alu/srawx.md

srawx — Shift Right Algebraic Word

Category: Integer ALU · Form: X · Opcode: 0x7c000630

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
sraw	srawx	—	Shift Right Algebraic Word
sraw.	srawx	Rc=1	Shift Right Algebraic Word

Syntax

sraw[Rc] [RA], [RS], [RB]

Encoding

srawx — form X

• Opcode word: 0x7c000630
• Primary opcode (bits 0–5): 31
• Extended opcode: 792
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	srawx: read	Source GPR (alias for RD in some stores).
RB	srawx: read	Source GPR.
RA	srawx: write	Source GPR (r0–r31).
CR	srawx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
CA	srawx: write	XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions.

Register Effects

srawx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA, CA
• Writes (conditional): CR

Status-Register Effects

• srawx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[CA] ← carry-out of the add / borrow-in of the subtract (always).

Operation (pseudocode)

n <- (RB)[58:63]
RA <- ((RS)[32:63] >>a n) sign-extended
CA <- 1 if (signed RS < 0) && any_bit_shifted_out else 0

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

srawx

• Canary XML: tools/ppc-instructions.xml — search for mnem="srawx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:1262
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:221
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:955

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_srawx(PPCHIRBuilder& f, const InstrData& i) {
  // n <- rB[59-63]
  // r <- ROTL32((RS)[32:63], 64-n)
  // m <- MASK(n+32, 63)
  // s <- (RS)[32]
  // RA <- r&m | (i64.s)&¬m
  // CA <- s & ((r&¬m)[32:63]≠0)
  // if n == 0: rA <- sign_extend(rS), XER[CA] = 0
  // if n >= 32: rA <- 64 sign bits of rS, XER[CA] = sign bit of lo_32(rS)
  Value* rt = f.Truncate(f.LoadGPR(i.X.RT), INT32_TYPE);
  Value* sh =
      f.And(f.Truncate(f.LoadGPR(i.X.RB), INT8_TYPE), f.LoadConstantInt8(0x3F));
  Value* clamp_sh = f.Min(sh, f.LoadConstantInt8(0x1F));
  Value* v = f.Sha(rt, f.Min(sh, clamp_sh));

  // CA is set if any bits are shifted out of the right and if the result
  // is negative.
  Value* ca =
      f.And(f.IsTrue(f.Shr(rt, 31)), f.CompareNE(f.Shl(v, clamp_sh), rt));
  f.StoreCA(ca);

  v = f.SignExtend(v, INT64_TYPE);
  f.StoreGPR(i.X.RA, v);
  if (i.X.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• 32-bit arithmetic right shift, sign-extended to 64. RA ← ((i32)RS >> n) sign-extended, with XER[CA] set when RS[32] = 1 (negative) AND any low bit was shifted out.
• Shift count is 6 bits, RB[58:63]. Counts ≥ 32 saturate: RA = -1 (all-ones, sign-extended) if RS < 0, else 0. Xenia handles this in three branches (interpreter.rs:432-444).
• SH = 0 sign-extends RS to 64 bits and clears XER[CA] — like extsw, but additionally writing CA.
• Result is always sign-extended to 64 bits. RA[0:31] matches the sign of RA[32]. This is the key difference from srwx (zero-extension).
• Rc=1 CR0 update truncates to 32 bits in xenia-rs. interpreter.rs:443 — but since the result is sign-extended, the low 32 bits' sign matches the full 64-bit sign, so spec and xenia agree here.
• Used with addzex for signed divide by 2^n rounding toward zero.
• No OE bit.

Related Instructions

• srawix — immediate-shift form.
• sradx, sradix — 64-bit arithmetic right shifts.
• srwx — 32-bit logical right shift (no XER[CA]).
• addzex — companion for divide-rounding idiom.
• slwx — left shift.

IBM Reference

• AIX 7.3 — sraw (Shift Right Algebraic Word)