Sylpheed/tools/ppc-manual/fpu/fcfidx.md

fcfidx — Floating Convert From Integer Doubleword

Category: Floating-Point · Form: X · Opcode: 0xfc00069c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fcfid	fcfidx	—	Floating Convert From Integer Doubleword
fcfid.	fcfidx	Rc=1	Floating Convert From Integer Doubleword

Syntax

fcfid[Rc] [FD], [FB]

Encoding

fcfidx — form X

• Opcode word: 0xfc00069c
• Primary opcode (bits 0–5): 63
• Extended opcode: 846
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FB	fcfidx: read	Source B floating-point register.
FD	fcfidx: write	Destination floating-point register.
CR	fcfidx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fcfidx: write	Floating-Point Status and Control Register.

Register Effects

fcfidx

• Reads (always): FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fcfidx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fcfidx

• Canary XML: tools/ppc-instructions.xml — search for mnem="fcfidx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:253
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:67
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:1029

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_fcfidx(PPCHIRBuilder& f, const InstrData& i) {
  // frD <- signed_int64_to_double( frB )
  Value* v = f.Convert(f.Cast(f.LoadFPR(i.X.RB), INT64_TYPE), FLOAT64_TYPE);
  f.StoreFPR(i.X.RT, v);
  f.UpdateFPSCR(v, i.X.Rc);
  return 0;
}

Special Cases & Edge Conditions

• 64-bit signed integer → binary64. Reads FRB as a 64-bit signed integer (the bits, interpreted as i64) and converts it to IEEE-754 binary64. Canary: f.Convert(f.Cast(FRB, INT64), FLOAT64).
• Loss of precision. binary64 has 53 bits of significand, so i64 values with magnitude > 2^53 lose low-order bits, raising FPSCR[XX, FX] on hardware. Canary rounds per the current rounding mode but raises no FPSCR bits (UpdateFPSCR is a stub).
• Always exact for |x| <= 2^53. Within ±9,007,199,254,740,992 the conversion is bit-exact.
• Rounding mode. Uses FPSCR[RN], default nearest-even. Canary's x64 backend converts with vcvtsi2sd, which rounds under the host MXCSR — and Canary loads that from FPSCR[RN] whenever the guest writes it through mtfsf/mtfsfi.
• No NaN/∞ generation. All i64 inputs map to finite f64 outputs (the largest i64 is well below f64::MAX).
• FPSCR side effects. Hardware updates FPRF (result class) and may set XX/FX on inexact. Canary does not compute them: its UpdateFPSCR is a stub that clears FEX and VX, leaves every other FPSCR bit unchanged and, with Rc=1, writes CR1 as all zeros.
• Rc=1 (fcfid.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• Encoding. X-form, primary 63, XO 846. Reads FRB only.
• Common pairing. Used after lfd of a stored i64 to bring an integer into the FP pipeline for arithmetic; the inverse direction is fctidx / fctidzx.

Related Instructions

• fctidx, fctidzx — inverse direction (binary64 → 64-bit integer, current rounding / round-toward-zero).
• fctiwx, fctiwzx — 32-bit integer conversion variants.
• frspx — round to single precision; commonly chained after fcfid to produce a float.
• lfd, stfd — load/store doubleword used to move integer values between GPR and FPR via memory.
• mffsx, mtfsfx — control rounding mode used by the conversion.

IBM Reference

• AIX 7.3 — fcfid (Floating Convert From Integer Doubleword)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (integer→FP conversion semantics).