Sylpheed/tools/ppc-manual/alu/addic.md

addic — Add Immediate Carrying

Category: Integer ALU · Form: D · Opcode: 0x30000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
addic	addic	—	Add Immediate Carrying

Syntax

addic [RD], [RA], [SIMM]

Encoding

addic — form D

• Opcode word: 0x30000000
• Primary opcode (bits 0–5): 12
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

Operands

Field	Role	Description
RA	addic: read	Source GPR (r0–r31).
SIMM	addic: read	16-bit signed immediate. Sign-extended to 64 bits before use.
RD	addic: write	Destination GPR.
CA	addic: write	XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions.

Register Effects

addic

• Reads (always): RA, SIMM
• Reads (conditional): none
• Writes (always): RD, CA
• Writes (conditional): none

Status-Register Effects

• addic: XER[CA] ← carry-out of the add / borrow-in of the subtract (always).

Operation (pseudocode)

RT <- (RA) + EXTS(SIMM)
CA <- carry_out

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

addic

• Canary XML: tools/ppc-instructions.xml — search for mnem="addic"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:117
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:11
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:451

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_addic(PPCHIRBuilder& f, const InstrData& i) {
  // RT <- (RA) + EXTS(SI)
  // CA <- carry bit
  Value* ra = f.LoadGPR(i.D.RA);
  Value* v = f.Add(ra, f.LoadConstantInt64(XEEXTS16(i.D.DS)));
  f.StoreGPR(i.D.RT, v);
  f.StoreCA(AddDidCarry(f, ra, f.LoadConstantInt64(XEEXTS16(i.D.DS))));
  return 0;
}

Special Cases & Edge Conditions

• Immediate is sign-extended. SIMM is a 16-bit signed value extended to 64 bits before the add. So addic r3, r4, -1 adds 0xFFFFFFFFFFFFFFFF to r4 — it does not zero-extend.
• XER[CA] always written. Unlike addi, this instruction exists to seed a multi-word add chain with an immediate. Carry-out is computed with the same result < ra unsigned-overflow check as addcx.
• No Rc bit available. This is the non-record form. For a record-form variant that also updates CR0, use addicx (addic.).
• No OE bit either. addic cannot raise / observe signed overflow — only the carry. If you need XER[OV] you must use the XO-form addcx with OE=1.
• RA = 0 reads register r0. Unlike addi, addic does not treat the RA field of zero as a literal zero. The PowerISA gives this instruction the regular RA semantics, not RA0.
• Subtract immediate carrying via negation. There is no subic mnemonic; assemblers synthesise subic RT, RA, value as addic RT, RA, -value (when value fits in 16 bits signed).

Related Instructions

• addicx — same operation plus Rc=1 CR0 update.
• addi — D-form add immediate without XER[CA].
• addis — shifted form (immediate << 16).
• addcx — XO-form: register operands, sets XER[CA].
• subfic — D-form: RT ← SIMM − RA with XER[CA].

IBM Reference

• AIX 7.3 — addic (Add Immediate Carrying)